MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 235

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1.4
The DMA Enable Error Interrupt High and Low (DMAEEIH and DMAEEIL) registers provide a bit map
for the implemented 64 channels to enable the error interrupt signal for each channel. DMAEEIH supports
channels 63–32, while DMAEEIL covers channels 31–00. The state of any given channel’s error interrupt
enable is directly affected by writes to this register; it is also affected by writes to the DMASEEI and
DMACEEI registers. The DMASEEI and DMACEEI registers are provided so that the error interrupt
enable for a single channel can easily be modified without the need to perform a read-modify-write
sequence to the DMAEEIH or DMAEEIL registers.
Freescale Semiconductor
Address: Base + 0x0008
Address: Base + 0x000C
Reset
Reset
Reset
Reset
ERQn
Field
W
W
W
W
R ERQ
R ERQ
R ERQ
R ERQ
63
47
31
15
16
16
0
0
0
0
0
0
DMA Enable Error Interrupt (DMAEEIH, DMAEEIL)
Enable DMA Request n
0 The DMA request signal for channel n is disabled.
1 The DMA request signal for channel n is enabled.
ERQ
ERQ
ERQ
ERQ
62
46
30
14
17
17
0
0
0
0
1
1
ERQ
ERQ
ERQ
ERQ
61
45
29
13
18
18
0
0
Figure 9-3. DMA Enable Request Register High (DMAERQH)
0
0
2
2
Figure 9-4. DMA Enable Request Register Low (DMAERQL)
Table 9-6. DMAERQH and DMAERQL field descriptions
ERQ
ERQ
ERQ
ERQ
60
44
28
12
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
ERQ
ERQ
ERQ
ERQ
59
43
27
11
20
20
4
0
0
4
0
0
ERQ
ERQ
ERQ
ERQ
58
42
26
10
21
21
0
0
0
0
5
5
ERQ
ERQ
ERQ
ERQ
57
41
25
09
22
22
0
0
0
0
6
6
ERQ
ERQ
ERQ
ERQ
56
40
24
08
23
23
0
0
0
0
7
7
Description
ERQ
ERQ
ERQ
ERQ
55
39
23
07
24
24
8
0
0
8
0
0
ERQ
ERQ
ERQ
ERQ
54
38
22
06
25
25
9
0
0
9
0
0
ERQ
ERQ
ERQ
ERQ
53
37
21
05
10
26
10
26
0
0
0
0
ERQ
ERQ
ERQ
ERQ
52
36
20
04
11
27
11
27
0
0
0
0
Direct Memory Access (DMA)
ERQ
ERQ
ERQ
ERQ
51
35
19
03
12
28
12
28
0
0
0
0
Access: User read/write
Access: User read/write
ERQ
ERQ
ERQ
ERQ
50
34
18
02
13
29
13
29
0
0
0
0
ERQ
ERQ
ERQ
ERQ
49
33
17
01
14
30
14
30
0
0
0
0
ERQ
ERQ
ERQ
ERQ
48
32
16
00
15
31
15
31
9-15
0
0
0
0