MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 797

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.4.1.2
Two methods are available to move data into the SDHC data buffer when writing data to the card. One is
by using DMA through the SDHC DMA request signal, and the other is by using the CPU through the
STATUS[BUF_WR_RDY] bit (interrupt or polling).
The SDHC automatically asserts a DMA request when the data buffer is empty and it is ready to receive
new data. At the same time, SDHC sets the STATUS[BUF_WR_RDY] bit. The buffer write ready interrupt
is generated if enabled by software.
The data buffer accumulates the data written until it fills. The SDHC does not start writing to the card until
a data buffer size is full. Then, the SDHC starts a transmission when the SD bus is ready for a new transfer.
When the other data buffer is empty and more data can be transferred, SDHC asserts a new DMA request
and sets the STATUS[BUF_WR_RDY] bit. See
28.4.1.3
Two methods are available to fetch data from the buffer when data is read from the card. One is by using
DMA through the SDHC DMA request signal, and the other is by using CPU through the
BUF_READ_RDY (STATUS[7]) bit (interrupt or polling).
The SDHC asserts a DMA request when the data buffer is full and it is ready for DMA/CPU to fetch data
out of the data buffer. At the same time, SDHC sets the BUF_READ_RDY (STATUS[7]) bit. The buffer
read ready interrupt is generated if enabled by software.
SDHC only starts receiving data when either of the two data buffers is empty. The buffer accumulates data
read from the card until it fills. SDHC asserts a DMA request when either one of the data buffers is full.
For multiple block data transfers, while the DMA/CPU moves data by reading the DBA register, SDHC
receives data into the other buffer if empty and the SD bus is ready. If the DMA/CPU does not keep up
with reading data out of the buffers, SDHC stops the SD_CLK at the block gap to avoid an overflow
situation.
28.4.1.4
Buffer sizes must be known during data transfers. In SDHC, both data buffers are 64 bytes in size.
However, each data buffer is divided into four 16-byte containers that correspond to the four data lines of
the SD bus. Therefore, the data buffer size is 64 bytes in 4-bit SD mode and 16 bytes in 1-bit SD mode.
During multi-block data transfer, block length should be an integer multiple of the buffer size. The buffer
is ready to be read by CPU/DMA when either of the buffers is full (STATUS[YBUF_FULL] or
STATUS[XBUF_FULL] is set, and STATUS[BUF_READ_READY] is set). The buffer would be ready
to write by CPU/DMA (STATUS[YBUF_EMPTY] or STATUS[XBUF_EMPTY] is set, and
STATUS[BUF_WR_RDY] is set) when the full buffer of data are fetched out of the buffer. The buffer
ready status bit and DMA request are set accordingly.
For single block data transfers when the block length is smaller than the buffer size or when the block
length is not an integer multiple times that of the buffer size, the data size may need to be written to the
buffer or to be fetched out of the buffer in smaller records. In this case, the buffer would be full (SDHC set
STATUS[YBUF_FULL] or STATUS[XBUF_FULL]) when these data are written to the buffer. The buffer
Freescale Semiconductor
Write Operation Sequence
Read Operation Sequence
Data Buffer Size
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 28.4.2.1, “DMA Request.”
Secure Digital Host Controller (SDHC)
28-25