MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 860

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.4.12 Transmit FIFO Tuning Controls (USB_TXFILLTUNING) Register
The Transmit FIFO Tuning Controls (USB_TXFILLTUNING) register controls and dynamically changes
the burst size used during data movement on device DMA transfers. It is only used in host mode.
The fields in this register control performance tuning associated with how the module posts data to the TX
latency FIFO before moving the data onto the USB bus. The specific areas of performance include how
much data to post into the FIFO and an estimate for how long that operation should take in the target
system.
Definitions:
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure
T
the pre-fill operation the time remaining in the [micro]frame is < T
is tried at a later time. Although this is not an error condition and the module eventually recovers, a mark
is made in the scheduler health counter to show the occurrence of a back-off event. When a back-off event
is detected, the partial packet fetched may need to be discarded from the latency buffer to make room for
periodic traffic that begins after the next SOF. Too many back-off events can waste bandwidth and power
on the system bus and should be minimized (not necessarily eliminated). Use of the TSCHHEALTH (T
parameter described below minimizes back-offs. This register is not defined in the EHCI specification.
32-32
p
TXPBURST
RXPBURST
remains before end of the [micro]frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during
Field
T
T
T
T
T
s
0
1
ff
p
= Total Packet Flight Time (send-only) packet (T
= Standard packet overhead
= Time to send data payload
= Total Packet Time (fetch and send) packet (T
= Time to fetch packet into TX FIFO up to specified level.
(Non-EHCI)
Programmable TX Burst Length. This register represents the maximum length of a burst in 32-bit words while
moving data from system memory to the USB bus.
If the BURSTSIZE bitfield of the USB_SBUSCFG register is non-zero, the TXPBURST bitfield returns the
value of the INCRx length.
Programmable RX Burst Length. This register represents the maximum length of a burst in 32-bit words while
moving data from the USB bus to system memory.
If the BURSTSIZE bitfield of the USB_SBUSCFG register is non-zero, the RXPBURST bitfield returns the
value of the INCRx length.
Table 32-26. USB_BURSTSIZE field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
p
s
= T
= T
ff
0
+ T
+ T
s
, packet attempt ceases and the packet
s
)
1
)
Freescale Semiconductor
ff
)