MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 314

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRAM Controller
11-6
ON DIE TERMINATE
QUART DQS DLY
HALF DQS DLY
EARLY ODT
WDLY[2:0]
RDLY[3:0]
Field
Table 11-2. DDR_SYS_CONFIG field descriptions (continued)
This field controls the expected delay between sending a read command to the DRAM and receiving
the read data from the DRAM.
RDLY, HALF DQS DLY, and QUART DQS delay together to code for t
The t
See
t
input of the READ command. Required t
between the DRAM and the device, and the type of DRAM used.
programming t
This field is an extra field to control the expected read delay between issuing the read command and
getting read data from the DRAM. This field offers 1/2 CSB clock granularity when programming the
delay. See description of field RDLY for details.
This field is an extra field to control the expected read delay between issuing the read command, and
getting read data from the DRAM. This field offers 1/4 csb clock granularity when programming the
delay. See the description of the RDLY bitfield.
This field controls the write latency (WL) for write commands.
This bit needs to be set if write latency is 1 (WDLY[2:0] = 001) and on die termination is used with
DDR2 DRAM. It makes sure the DRAM controller asserts the ODT signal going to the DRAM one
clock ahead of issuing the write command.
This bit controls on-die termination (ODT) in the controller. If this bit is 1, the internal pads generate
ODT during read. If the bit is 0, no ODT is provided. The ODT in the DRAM is controlled via the
DRAM internal configuration registers. Please consult DRAM data sheet for it.
DQSEN
Figure
DQSEN
should be selected so the L-H transition of DQS enable is always in the preamble of the DQS
MPC5125 Microcontroller Reference Manual, Rev. 2
11-3. Timing is internally compensated, and is referred to timing at the device pins.
is the delay between the read command and when the internal DQS enable goes high.
DQSEN.
WDLY[2:0]
0b001
0b010
0b011
0b100
Other values of WDLY are reserved.
DQSEN
Write Latency (CSB Clocks)
Description
value depends on the CAS latency (CL), the distance
1
2
3
4
Table 11-3
DQSEN
Freescale Semiconductor
.
gives the detail on