MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 847

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Address: Base + 0x140
Reset
Reset
ATDTW
SUTW
ASPE
Field
ASP
FS2
ITC
LR
W
W
R
R
FS2
16
0
0
0
0
ATDT
Interrupt Threshold Control. The system software uses this field to set the maximum rate at which the module
issues interrupts. ITC contains the maximum interrupt interval measured in microframes. Valid values are
shown below.
0x00 Immediate (no threshold)
0x01 1 microframe
0x02 2 microframes
0x04 4 microframes
0x08 8 microframes
0x10 16 microframes
0x20 32 microframes
0x40 40 microframes
See bit 3:2 below. This is a non-EHCI bit.
Add dTD TripWire. This is a non-EHCI bit is present on the OTG module only. This bit acts as a semaphore
when a dTD is added to an active (primed) endpoint. This bit is set and cleared by software. This bit is also
cleared by hardware when the state machine is in a hazard region where adding a dTD to a primed endpoint
may go unrecognized. More information on the use of this bit is described in
Operation,”
Setup TripWire. This is a non-EHCI bit present on the OTG module only. This bit acts as a semaphore when
the 8 bytes of setup data read extracted from a QH by the DCD. If the setup lockout mode is off (See the
USB_USBMODE register), a hazard exists when new setup data arrives and the DCD is copying setup from
the QH for a previous setup packet. This bit is set and cleared by software or cleared by hardware. More
information on the use of this bit is described in
Asynchronous Schedule Park Mode Enable. Software uses this bit to enable or disable Park mode.
0 Disabled.
1 Enabled.
Asynchronous Schedule Park Mode Count. It contains a count of the number of successive transactions the
host controller is allowed to execute from a high-speed queue head on the asynchronous schedule before
continuing traversal of the asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write a 0
to this field when park mode enable is a 1 as this results in undefined behavior.
Light Host/Device Controller Reset (OPTIONAL). Not Implemented. Always 0.
W
17
0
0
0
1
SUT
W
18
0
0
0
2
of this manual.
Figure 32-16. USB Command (USB_USBCMD) Register
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-16. USB_USBCMD field descriptions
ASPE
20
4
0
0
0
21
0
0
0
0
5
22
0
0
0
6
ASP
23
0
0
0
7
Description
Section 32.8.10.1, “Device Operation,”
LR
24
8
0
0
IAA
25
9
0
0
Universal Serial Bus Interface with On-The-Go
ASE
10
26
0
0
PSE
11
27
0
0
Section 32.8.10.1, “Device
ITC
FS1
12
28
0
0
Access: User read/write
of this manual.
FS0
13
29
0
0
RST
14
30
0
0
32-19
RS
15
31
0
0