MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 910

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
1
2
3
32.6.3
The host controller executes transactions for devices using a simple, shared-memory schedule. The
schedule is comprised of a few data structures, organized into two distinct lists. The data structures provide
the maximum flexibility required by USB, minimize memory traffic, and hardware/software complexity.
System software maintains two schedules for the host controller: a periodic schedule and an asynchronous
schedule. The root of the periodic schedule is the USB_PERIODICLISTBASE register. See
Section 32.2.4.6, “Periodic Frame List Base Address (USB_PERIODICLISTBASE) Register,”
32-82
Port disabled, resume K-State received
Port suspended, Resume K-State received
Port is enabled, disabled or suspended, and the
port's WKDSCNNT_E bit is set. A disconnect is
detected.
Port is enabled, disabled or suspended, and the
port's WKDSCNNT_E bit is cleared. A
disconnect is detected.
Port is not connected and the port's WKCNNT_E
bit is a one. A connect is detected.
Port is not connected and the port's WKCNNT_E
bit is a zero. A connect is detected.
Port is connected and the port's WKOC_E bit is
a one. An over-current condition occurs.
Port is connected and the port's WKOC_E bit is
a zero. An over-current condition occurs.
Hardware interrupt issued if port change interrupt enable bit in the USB_USBINTR register is set.
ME# asserted if enabled. PPME Status must always be set.
PME# not asserted.
Port Status and Signaling Type
Schedule Traversal Rules
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-69. Behavior During Wake-up Events
No effect.
Resume reflected downstream on signaled port.
Force port resume status bit in USB_PORTSCn
register is set. Port change detect bit in
USB_USBSTS register is set.
Depending in the initial port state, the
USB_PORTSCn connect and enable status bits
are cleared, and the connect change status bit is
set. Port change detect bit in the USB_USBSTS
register is set.
Depending on the initial port state, the
USB_PORTSCn connect and enable status bits
are cleared, and the connect change status bit is
set. Port change detect bit in the USB_USBSTS
register is set.
USB_PORTSCn connect status and connect
status change bits are set. Port change detect bit
in the USB_USBSTS register is set.
USB_PORTSCn connect status and connect
status change bits are set. Port change detect bit
in the USB_USBSTS register is set.
USB_PORTSCn over-current active,
over-current change bits are set. If port
enable/disable bit is a one, it is cleared. Port
change detect bit in the USB_USBSTS register is
set
USB_PORTSCn over-current active,
over-current change bits are set. If port
enable/disable bit is a one, it is cleared. Port
change detect bit in the USB_USBSTS register is
set.
Signaled Port Response
Freescale Semiconductor
1
N/A
1
1
1
1
1
1
D0
,
,
,
,
,
,
,
Device State
2
3
2
3
2
3
2
for more
not D0
N/A
2
2
3
2
3
2
3