MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet
MPC5125YVN400
Specifications of MPC5125YVN400
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MPC5125YVN400 Summary of contents
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... On-chip temperature sensor • IC Identification module (IIM) This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008–2009. All rights reserved. Document Number: MPC5125 Rev. 3, 11/2009 MPC5125 324 TEPBGA ...
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... Pullup/Pulldown Resistor Requirements . . . . . . . . . . . 83 5.4.1 Pulldown Resistor Requirements for TEST Pin 83 5.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.1 JTAG_TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.2 e300 COP / BDM Interface . . . . . . . . . . . . . . . . 83 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2 Mechanical Dimensions Product Documentation Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 MPC5125 Microcontroller Data Sheet, Rev Power Supply Filtering . 82 DD Freescale Semiconductor ...
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... Note: Not all options are available on all devices. Refer to Figure 1. MPC5125 Orderable Part Number Description Table 1 shows the orderable part numbers for the MPC5125. 1 Freescale Part Number MPC5125YVN400 MPC5125 324TEPBGA package NOTES: 1 All packaged devices are PPC5125, rather than MPC125, until product qualifications are complete. 2 ...
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... Figure 2. Simplified MPC5125 Block Diagram 4 Display SDR, Mobile DDR, DDR1/2 Memory DIU Multi-Port Memory Controller 32 KB SRAM MPC5125 e300 Power Architecture 32 KB instruction / 32 KB data cache MPC5125 Microcontroller Data Sheet, Rev. 3 FEC1 FEC2 USB1 ULPI USB2 ULPI DMA 64-Channel Freescale Semiconductor ...
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... USB1_ AA VSS TXD_2 RXD_3 RXD_1 O NEXT FEC1_ FEC1_ FEC1_ USB1_ USB1_ AB VSS RX_CL RXD_0 RX_DV DATA7 DATA3 K Figure 3. Ball Map for the MPC5125 324 TEPBGA Package Freescale Semiconductor RTC_X RTC_X SYS_X SYS_X AVDD_ PSC0_ PSC0_ TALO TALI TALI TALO SPLL 1 2 AVSS_ ...
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Pin Muxing and Reset States Table 2 provides the pinout listing for the MPC5125. Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset GPIO00 — ALT0 GPIO00 ALT1 — ALT2 — ALT3 — GPIO01 — ALT0 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset SPLL_ANAVIZ — ALT0 SPLL_ANAVIZ ALT1 — ALT2 — ALT3 — TMPS_ANAVIZ — ALT0 TMPS_ANAVIZ ALT1 — ALT2 — ALT3 — SYS_XTALI — ALT0 SYS_XTALI ALT1 — ALT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MVTT0 — ALT0 MVTT0 ALT1 — ALT2 — ALT3 — MVTT1 — ALT0 MVTT1 ALT1 — ALT2 — ALT3 — MVTT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ03 0x00 ALT0 MDQ03 IO_CON- ALT1 — TROL_MEM ALT2 — ALT3 — MDQ04 0x00 ALT0 MDQ04 IO_CON- ALT1 — TROL_MEM ALT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ11 0x00 ALT0 MDQ11 IO_CON- ALT1 — TROL_MEM ALT2 — ALT3 — MDQ12 0x00 ALT0 MDQ12 IO_CON- ALT1 — TROL_MEM ALT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ19 0x00 ALT0 MDQ19 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPT1[3] MDQ20 0x00 ALT0 MDQ20 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ27 0x00 ALT0 MDQ27 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPIO24 MDQ28 0x00 ALT0 MDQ28 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDM3 0x00 ALT0 MDM3 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPIO30 MDQS0 0x00 ALT0 MDQS0 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MA00 0x00 ALT0 MA00 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MA01 0x00 ALT0 MA01 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MA08 0x00 ALT0 MA08 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MA09 0x00 ALT0 MA09 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MCK 0x00 ALT0 MCK ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MCK 0x00 ALT0 MCK ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MCKE 0x00 ALT0 MCKE ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset LPC_ACK_B 0x08 ALT0 LPC_ACK/LPC_BURST ALT1 NFC_CE1 STD_PU ALT2 LPC_CS1 ALT3 GPIO08 LPC_AX03 0x09 ALT0 LPC_AX03/LPC_TS ALT1 NFC_CE2 STD_PU ALT2 LPC_CS2 ALT3 — EMB_AD00 0x2C ALT0 LPC_AD00/NFC_AD00 ALT1 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD05 0x27 ALT0 LPC_AD05/NFC_AD05 ALT1 — STD_PU ALT2 RST_CONF_COREPLL6 ALT3 — EMB_AD06 0x26 ALT0 LPC_AD06/NFC_AD06 ALT1 — STD_PU ALT2 RST_CONF_COREPLL5 ALT3 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD13 0x1F ALT0 LPC_AD13/NFC_AD13 ALT1 PSC2_2 STD_PU ALT2 RST_CONF_PREDIV1 ALT3 GPIO23 EMB_AD14 0x1E ALT0 LPC_AD14/NFC_AD14 ALT1 PSC2_1 STD_PU ALT2 RST_CONF_PREDIV2 ALT3 GPIO22 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD21 0x17 ALT0 LPC_AD21/LPC_A06 ALT1 — STD_PU ALT2 — ALT3 GPIO19 EMB_AD22 0x16 ALT0 LPC_AD22/LPC_A07 ALT1 — STD_PU ALT2 RST_CONF_LPC_TS ALT3 GPIO18 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD29 0x0F ALT0 LPC_AD29/LPC_A14 ALT1 — STD_PU ALT2 — ALT3 GPIO11 EMB_AD30 0x0E ALT0 LPC_AD30/LPC_A15 ALT1 CAN_CLK STD_PU_ST ALT2 — ALT3 GPIO10 EMB_AD31 0x0D ALT0 LPC_AD31/LPC_A16 ALT1 PSC_MCLK_IN ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_CLK 0x02F ALT0 DIU_CLK ALT1 PSC4_0 STD_PU ALT2 USB1_DATA0 ALT3 LPC_AX04 DIU_DE 0x030 ALT0 DIU_DE ALT1 PSC4_1 STD_PU ALT2 USB1_DATA1 ALT3 LPC_AX05 DIU_HSYNC 0x031 ALT0 DIU_HSYNC ALT1 PSC4_2 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD04 0x037 ALT0 DIU_LD04 ALT1 PSC5_1 STD_PU ALT2 USB1_DATA6 ALT3 LPC_AX09 DIU_LD05 0x038 ALT0 DIU_LD05 ALT1 PSC5_2 STD_PU ALT2 USB1_DATA7 ALT3 GPIO34 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD12 0x03F ALT0 DIU_LD12 ALT1 PSC6_4 STD_PU ALT2 USB2_DATA0 ALT3 GPT2[0] DIU_LD13 0x040 ALT0 DIU_LD13 ALT1 PSC7_0 STD_PU ALT2 USB2_DATA1 ALT3 GPT2[1] ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD20 0x047 ALT0 DIU_LD20 ALT1 PSC8_0 STD_PU ALT2 USB2_DATA6 ALT3 GPT2[6] DIU_LD21 0x048 ALT0 DIU_LD21 ALT1 PSC8_1 STD_PU ALT2 USB2_DATA7 ALT3 GPT2[7] ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset CAN1_RX — ALT0 CAN1_RX ALT1 — ALT2 — ALT3 — CAN2_RX — ALT0 CAN2_RX ALT1 — ALT2 — ALT3 — CAN1_TX 0x4D ALT0 CAN1_TX ALT1 PSC9_0 STD_PU_ST ALT2 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset FEC1_CRS 0x55 ALT0 FEC1_CRS ALT1 PSC2_4 STD_PU ALT2 USB2_DATA4 ALT3 GPIO55 FEC1_TX_ER 0x56 ALT0 FEC1_TX_ER ALT1 PSC3_0 STD_PU ALT2 USB2_DATA5 ALT3 GPIO56 FEC1_RXD_1 0x57 ALT0 FEC1_RXD_1/RMII_RX1 ALT1 PSC3_1 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset FEC1_TXD_0 0x5D ALT0 FEC1_TXD_0/RMII_TX0 ALT1 — STD_PU_ST ALT2 NFC_R/B1 ALT3 GPIO63 FEC1_TX_CLK 0x5E ALT0 FEC1_TX_CLK/RMII_REF_CLK ALT1 PSC0_0 STD_PU_ST ALT2 — ALT3 GPIO04 FEC1_RX_CLK 0x5F ALT0 FEC1_RX_CLK ALT1 PSC0_1 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset USB1_DATA2 0x65 ALT0 USB1_DATA2 ALT1 PSC1_2 STD_PU ALT2 FEC2_MDC/RMII_MDC ALT3 — USB1_DATA3 0x66 ALT0 USB1_DATA3 ALT1 PSC1_3 STD_PU ALT2 FEC2_RX_ER/RMII_RX_ER ALT3 — USB1_DATA4 0x67 ALT0 USB1_DATA4 ALT1 PSC1_4 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset USB1_NEXT 0x6D ALT0 USB1_NEXT ALT1 — STD_PU ALT2 FEC2_TX_EN/RMII_TX_EN ALT3 GPIO09 USB1_DIR 0x6E ALT0 USB1_DIR ALT1 — STD_PU_ST ALT2 FEC2_COL ALT3 GPIO10 SDHC1_CLK 0x6F ALT0 SDHC1_CLK ALT1 NFC_CE1 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset PSC_MCLK_IN 0x75 ALT0 PSC_MCLK_IN ALT1 — STD_PU_ST ALT2 — ALT3 GPIO14 PSC0_0 0x76 ALT0 PSC0_0 ALT1 SDHC2_CMD STD_PU ALT2 GPT1[0] ALT3 GPIO15 PSC0_1 0x77 ALT0 PSC0_1 ALT1 SDHC2_D0 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset PSC1_2 0x7D ALT0 PSC1_2 ALT1 TPA2 STD_PU ALT2 GPT1[7] ALT3 IRQ1 PSC1_3 0x7E ALT0 PSC1_3 ALT1 CKSTP_IN STD_PU ALT2 NFC_R/B2 ALT3 GPIO19 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset TMS — ALT0 TMS ALT1 — ALT2 — ALT3 — TRST — ALT0 TRST ALT1 — ALT2 — ALT3 — HRESET — ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset TEST — ALT0 TEST ALT1 — ALT2 — ALT3 — NOTES: 1 Pins controlled by the STD_PU_ST register have a Schmitt trigger input; pins controlled by the STD_PU ...
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... This table indicates only the pins with a permanently enabled internal pullup, pulldown, or Schmitt trigger. Most digital I/O pins can be configured to enable internal pullup, pulldown, or Schmitt trigger. See the MPC5125 Reference Manual (MPC5125RM), “I/O Control” chapter. Freescale Semiconductor Function Description Power ...
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... V + 0.3 V DD_IO − 0 0.3 V DD_IO_MEM − 0 0.3 V BAT — — − 150 C 1 Typ Max Unit 1.4 1. — — Freescale Semiconductor SpecID D1.1 D1.2 D1.15 D1.16 D1.3 D1.4 D1.5 D1.6 D1.7 D1.9 D1.10 D1.11 D1.12 D1.13 D1.14 SpecID D2.1 D2.2 ...
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... VBAT should not be supplied by a battery of voltage less than 3.0 V. 4.1.3 DC Electrical Specifications Table 6 gives the DC electrical characteristics for the MPC5125 at recommended operating conditions. Characteristic Condition Input high voltage Input type = TTL V Input high voltage Input type = TTL V DD_IO_MEM_DDR Freescale Semiconductor 1 Sym Min V 3.0 DD_IO V 2.3 DD_IO_MEM_DDR V 1.7 DD_IO_MEM_DDR2 ...
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... V DD_IO 1.94 V — V — — V Freescale Semiconductor D3.3 D3.4 D3.33 D3.5 D3.6 D3.7 D3.8 D3.9 D3.10 D3.11 D3.34 D3.12 D3.13 D3.14 D3.15 D3.16 D3.17 D3.18 D3.19 D3.20 D3.21 D3.22 D3.23 ...
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... All injection current is transferred to V power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. Freescale Semiconductor Sym 7 V 0.8 × VDD_IO_MEM ...
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... TT DD_IO_MEM + 50 mV for all modes. DD_IO_MEM – 450 mV for all modes. DD_IO_MEM Min Max Unit 2000 — V 200 — V 250 — V Freescale Semiconductor SpecID D3.41 D3.42 D3.43 D3.44 SpecID D3.45 D3.46 D3.47 D3.48 D3.49 D3.50 SpecID D4.1 D4.2 D4.3 ...
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... PLL/OSC Power Supplies (AV Operational Deep-sleep Unloaded I/O Power Supplies (V Operational Deep-sleep NOTES: 1 Typical core power is measured Operational power is measured while running an entirely cache-resident program with floating-point multiplication instructions in parallel with DDR write operation. Freescale Semiconductor ) DD and AV DD_SPLL and V ) DD_IO_MEM DD_IO ∑ × × ...
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... θ MPC5125 Microcontroller Data Sheet, Rev ° ° Sym Value Unit SpecID R 35 °C/W θ °C/W θJA 29 °C/W θJMA R 22 °C/W θJMA — °C/W θJB — °C/W θJC Ψ 3 °C/W JT Freescale Semiconductor D6.1 D6.2 D6.3 D6.4 D6.5 D6.6 D6.7 Eqn. 3 ...
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... The MPC5125 system requires a system-level clock input SYS_XTALI. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent real-time clock (RTC) system. The MPC5125 clock generation uses two phase-locked loop (PLL) blocks. Freescale Semiconductor θ ...
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... MPC5125 Microcontroller Data Sheet, Rev. 3 Max Unit 35.0 MHz t t RISE FALL Min Max Units 64.1 28. (15 MHz) are taken from sys_xtal (MIN/MAX) Max Unit — kHz Freescale Semiconductor SpecID O1.1 SpecID O.1.2 O.1.3 O.1.4 O.1.5 SpecID O2.1 ...
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... PLL-relock time is the maximum amount of time required for the PLL lock after a stable V during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. Freescale Semiconductor Table 15. System PLL Specifications Sym ...
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... Table 17. Clock Frequencies Min Max 200 400 50 200 50 200 8.3 66 2.08 66 3.13 50 0.78 66 0.78 50 0.78 66 MPC5125 Microcontroller Data Sheet, Rev. 3 Units SpecID MHz A1.1 MHz A1.2 MHz A1.3 MHz A1.4 MHz A1.6 MHz A1.7 MHz A1.8 MHz A1.9 MHZ A1.10 Freescale Semiconductor ...
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... HRESET and SRESET must have a monotonous rise time. 3 The assertion of HRESET becomes active at power-on reset without any SYS_XTAL clock. The timing relationship can be seen in the following figures. Freescale Semiconductor , for more information on the clock subsystem. Section 4.1, “DC Electrical Table 18. Reset Rise / Fall Timing Min Max — ...
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... Electrical and Thermal Characteristics XTALI CLOCK PORESET HRESET SRESET t S_POR_CONF RST_CONF[31:0] ADDR[31:0] XTALI CLOCK PORESET HRESET SRESET RST_CONF[31:0] ADDR[31: HRVAL t SRVAL t EXEC t H_POR_CONF Figure 5. Power-Up Behavior t PORHold t HRVAL t S_POR_CONF t H_POR_CONF Figure 6. Power-On Reset Behavior MPC5125 Microcontroller Data Sheet, Rev SRVAL t EXEC Freescale Semiconductor ...
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... Time HRESET is asserted after a qualified reset occurs. HRVAL t Time SRESET is asserted after assertion of HRESET. SRVAL t Time between SRESET assertion and first core instruction fetch. EXEC t Reset configuration setup time before assertion of PORESET. S_POR_CONF Freescale Semiconductor t HRHOLD t HRVAL t SRVAL t HR_SR_Delay no new fetch of the RST_CONF Figure 7. HRESET Behavior ...
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... Table 19. Reset Timing (continued) Description Symbol Min t 2T PICWID to ensure proper operation in edge-triggered mode. PICWID MPC5125 Microcontroller Data Sheet, Rev. 3 Value SpecID (XTALI CLOCK) 1 cycle A3.15 4 cycles A3.16 4 cycles A3.17 4 cycles A3.18 1 cycles A3.19 Unit Spec ID ns A4.1 Section 4.1, “DC Freescale Semiconductor ...
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... At recommended operating conditions with V Parameter Clock cycle time MCK AC differential crosspoint voltage CK HIGH pulse width CK LOW pulse width Skew between MCK and DQS transitions Address and control output setup time relative to MCK rising edge Freescale Semiconductor Symbol Min t 6000 CK × 0.5)– 0. OX-AC ...
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... Max Unit Notes SpecID — ps × 0. DD_IO_MEM 1,3 0. 1,3 0. 2,3 0. 2,3 — ps 2,3 — ps 2,3 — ps 2,3 — − 600 1,2,3, 1500 Freescale Semiconductor A5.7 A5.8 A5.9 A5.10 A5.11 A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7 A5.8 A5.9 A5.10 A5.11 ...
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... To achieve better timing, balance the loading of DQS as MCK although DQS is not used in SDR mode. Figure 9 shows the DDR SDRAM write timing. MCK DQS DQ, DM(out) Freescale Semiconductor /2). DD_IO_MEM = 2.5 t (RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0) with DDR2 CK , the window position is shifted accordingly. ...
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... AC test load for the DDR bus. Output DQSQ DQSQ Figure 10. DDR Read Timing DQS DQSEN (MIN) t DQSEN (MAX) Figure 11. DDR Read Timing, DQSEN Figure 12. SDR AC Timing = 50 Ω Ω Figure 13. DDR AC Test Load MPC5125 Microcontroller Data Sheet, Rev DD_IO_MEM Freescale Semiconductor ...
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... Write burst ACK assertion after CS[x] assertion 14 t Write burst DATA valid 15 t Non-MUXed mode: asynchronous write 16 burst ADDR valid before write DATA valid t MUXed mode: ADDR cycle 17 t MUXed mode: ALE cycle 18 Freescale Semiconductor Table 25. LPC Timing Min WS) × t LPCck − LPCck OD − LPCck OD − t ...
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... LPCck t LPCck MPC5125 Microcontroller Data Sheet, Rev. 3 Max Units SpecID t ns LPCck — ns — ns (ALT × (AL × WS) ns × t LPCck (ALT × (AL × WS BBT/DS) × t LPCck (ALT × (AL × 2.5 WS BBT/DS)× t LPCck Freescale Semiconductor A7.20 A7.21 A7.22 A7.23 A7.23 A7.23 ...
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... ADDR TS OE R/W DATA (rd) ACK Figure 15. Timing Diagram — Non-MUXed Synchronous Read Burst Mode 4.3.6.1.3 Non-MUXed Synchronous Write Burst Mode LPC_CLK CS[ ADDR TS R/W DATA (wr) ACK Figure 16. Timing Diagram — Non-MUXed Synchronous Write Burst Freescale Semiconductor NOTE t 8 Valid Address Valid Address t 14 MPC5125 Microcontroller Data Sheet, Rev ...
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... Non-MUXed Asynchronous Write Burst Mode LPC_CLK CS[ ADDR[31:n+1] ADDR[n:0] TS R/W DATA (wr) ACK Figure 18. Timing Diagram — Non-MUXed Asynchronous Write Burst Valid Address (Page address) Valid Address Valid Address (Page address) Valid Address MPC5125 Microcontroller Data Sheet, Rev Valid Address Valid Address Freescale Semiconductor ...
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... ALE TS CS[x] OE ACK TSIZ[1:0] Figure 19. Timing Diagram — MUXed non-Burst Mode ACK is asynchronous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. Freescale Semiconductor NOTE MPC5125 Microcontroller Data Sheet, Rev. 3 Electrical and Thermal Characteristics Valid Write Data ...
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... ALE TS CS[x] OE R/W ACK Figure 20. Timing Diagram — MUXed Synchronous Read Burst 4.3.6.2.3 MUXed Synchronous Write Burst Mode LPC_CLK AD[31:0] (wr) Address t 18 ALE TS CS[x] R/W ACK Figure 21. Timing Diagram — MUXed Synchronous Write Burst MPC5125 Microcontroller Data Sheet, Rev Freescale Semiconductor ...
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... Ready to NFC_RE low RR t NFC_RE pulse width RP t READ cycle time RC t NFC_RE high hold time REH t Data input setup time IS Freescale Semiconductor × NFC_RATIO_H / 8 (ns × NFC_RATIO_L / 8 (ns) Min. value 2TH + TL – – 1 2TH + TL – – 1 2TH + – – – – ...
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... NFIO[7:0] NFC_ALE NFC_CE[3:0] NFC_WE NFIO[7: NFC_CE[3:0] NFC_WE NFIO[15: CLS command t DS Figure 22. Command Latch Cycle Timing t ALS address t DS Figure 23. Address Latch Cycle Timing data data Figure 24. Write Data Latch Timing MPC5125 Microcontroller Data Sheet, Rev CLH ALH data Freescale Semiconductor ...
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... RXD [ RX_DV, RX_ER to RX_CLK setup 1 t RX_CLK to RXD [ RX_DV, RX_ER hold 2 t RX_CLK pulse width high 3 t RX_CLK pulse width low 4 NOTES: 1 RX_CLK shall have a frequency of 25% of the data rate of the received signal. See the IEEE 802.3 specification. Freescale Semiconductor REH data ...
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... Unit — ns — 65% TX_CLK period 1 65% TX_CLK period Max Unit — 65% TX_CLK Period 1 65% TX_CLK Period Max Unit — 65% TX_CLK Period 1 65% TX_CLK Period Freescale Semiconductor SpecID A11.5 A11.6 A11.7 A11.8 SpecID A11.9 A11.10 A11.11 A11.12 SpecID A11.13 A11.14 A11.15 A11.16 ...
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... See the MPC5125 Reference Manual (MPC5125RM). 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5125 Reference Manual (MPC5125RM). Freescale Semiconductor ...
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... Setup time (control in, 8-bit data in Hold time (control in, 8-bit data in Output delay (control out, 8-bit data out Figure 31. ULPI Timing Diagram Description MPC5125 Microcontroller Data Sheet, Rev Min Max Units SpecID 15 — ns A12.1 — 6.0 ns A12.2 0.0 — ns A12.3 — 9.0 ns A12.4 Freescale Semiconductor ...
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... Clock fall time (full speed/high speed) SDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SDHC output delay SDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD7 SDHC input setup time SD8 SDHC input hold time Freescale Semiconductor SD4 SD2 SD5 MMCx_CLK SD3 MMCx_CMD MMCx_DAT_0 MMCx_DAT_2 ...
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... The default is active-high. The DIU_DE signal is always active-high. Also, pixel clock inversion and a flexible programmable pixel clock delay are also supported, programmed via the DIU Clock Config register (DCCR) in the system clock module. 68 LINE 3 LINE MPC5125 Microcontroller Data Sheet, Rev. 3 LINE n-1 LINE n m m-1 Freescale Semiconductor ...
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... Figure 35. TFT LCD Interface Timing Diagram — Vertical Sync Pulse Table 35 shows timing parameters of signals. Table 35. LCD Interface Timing Parameters — Pixel Level Sym Description t Display Pixel Clock Period PCP t HSYNC Pulse Width PWH t HSYNC Back Porch Width BPH Freescale Semiconductor t HSP t BPH VSP t BPV 2 3 ...
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... A15.4 ns A15.5 ns A15.6 PCP ns A15.7 ns A15.8 ns A15.9 ns A15.10 ns A15.11 HSP Table 36 lists the timing parameters. CSU DSU Max Unit × 0.5 × 0 A15.12 PCP × 0.5 × 0 A15.13 PCP — ns A15.14 — ns A15.15 — ns A15.16 — ns A15.17 Freescale Semiconductor SpecID SpecID ...
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... Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time that SCL or SDA takes to reach a high level depends on external signal capacitance and pullup resistor values. 4 Inter -peripheral Clock is defined in the MPC5125 Reference Manual (MPC5125RM). Freescale Semiconductor 2 C Input Timing Specifications — SCL and SDA Description 2 C Output Timing Specifications — ...
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... MPC5125 Microcontroller Data Sheet, Rev Mode Master Mode Typ Max Units — — — 7.9 ns — 7.9 ns — 8.4 ns — 8.4 ns — 9.3 ns — — ns Freescale Semiconductor SpecID A20.1 A20.2 A20.3 A20.4 A20.5 A20.6 A20.7 A20.8 ...
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... Frame sync setup time 4 Output data valid after clock edge 5 Input data setup time 6 Input data hold time NOTES: 1 Output timing is specified at a nominal 50 pF load. 2 Bit clock cycle time. Freescale Semiconductor 40.0 MPC5125 Microcontroller Data Sheet, Rev. 3 Electrical and Thermal Characteristics ...
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... MPC5125 Microcontroller Data Sheet, Rev Slave Mode 1 Min Typ Max Units — 81.4 — ns — 40.7 — ns — 40.7 — ns — — 13.0 ns — — 14.0 ns 1.0 — — ns 1.0 — — ns Freescale Semiconductor SpecID A20.15 A20.16 A20.17 A20.18 A20.19 A20.20 A20.21 ...
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... Sequential transfer delay, programable in the PSC CTUR / CTLR register 10 Clock falling time 11 Clock rising time NOTES: 1 Output timing is specified at a nominal 50 pF load. Freescale Semiconductor Figure 40. Timing Diagram — AC97 Mode Description MPC5125 Microcontroller Data Sheet, Rev. 3 Electrical and Thermal Characteristics ...
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... Description MPC5125 Microcontroller Data Sheet, Rev Min Max Units SpecID 30.0 — ns A20.37 15.0 — ns A20.38 1.0 — ns A20.39 1.0 — ns A20.40 1.0 — ns A20.41 — 14.0 ns A20.42 — 14.0 ns A20.43 0.0 — ns A20.44 30.0 — — A20.45 Freescale Semiconductor ...
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... Input data hold time 7 Slave disable lag time 8 Sequential transfer delay, programable in the PSC CTUR / CTLR register 9 Clock falling time 10 Clock rising time NOTES: 1 Output timing is specified at a nominal 50 pF load. Freescale Semiconductor Description MPC5125 Microcontroller Data Sheet, Rev. 3 Electrical and Thermal Characteristics ...
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... Output timing is specified at a nominal 50 pF load Description MPC5125 Microcontroller Data Sheet, Rev Min Max Units SpecID 30.0 — ns A20.56 15.0 — ns A20.57 0.0 — ns A20.58 — 14.0 ns A20.59 2.0 — ns A20.60 1.0 — ns A20.61 0.0 — ns A20.62 30.0 — ns A20.63 Freescale Semiconductor ...
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... Program time for fuse FUSEWR I Program current to program one fuse bit FUSEWR NOTES: 1 The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module. Freescale Semiconductor Description Table 47. Fusebox Timing Characteristics Description MPC5125 Microcontroller Data Sheet, Rev. 3 Electrical and Thermal Characteristics ...
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... MPC5125 Microcontroller Data Sheet, Rev. 3 Min Max Unit 0 25 MHz 40 — ns 1.08 — — — — — — ns 4.5 — Midpoint Voltage Numbers shown reference JTAG Timing Specification T Freescale Semiconductor SpecID A23.1 A23.2 A23.3 A23.4 A23.5 A23.6 A23.7 A23.8 A23.9 A23.10 A23.11 A23.12 A23.13 A23.14 ...
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... Data Outputs Figure 47. Timing Diagram — JTAG Boundary Scan TCK TDI, TMS TDO TDO Figure 48. Timing Diagram — Test Access Port Freescale Semiconductor 4 5 Numbers shown reference JTAG Timing Specification Table Figure 46. Timing Diagram — JTAG TRST 8 9 Numbers shown reference JTAG Timing Specification Table ...
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... Figure 49. Power Supply Filtering . All NC (no-connect) signals must remain unconnected. SS and V pins of the MPC5125 directly or via a resistor. SS MPC5125 Microcontroller Data Sheet, Rev. 3 supplies first in any order, and DD_IO_MEM s by more than 0 any time, including Figure 49 shows a recommendation for the AV device pin DD Freescale Semiconductor ...
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... The MPC5125 functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale standard COP / BDM interface. COP / BDM connector order. Freescale Semiconductor Figure 50. PORESET vs. TRST Table 49 gives the COP / BDM interface signals. The pin order shown reflects only the MPC5125 Microcontroller Data Sheet, Rev ...
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... External Pullup / Pulldown — — 10 kΩ Pullup I — — 10 kΩ Pullup O — — 10 kΩ Pullup O — — 10 kΩ Pullup O 10 kΩ Pullup O 10 kΩ Pullup O — — — kΩ Pullup O 10 kΩ Pullup O — O — I Freescale Semiconductor ...
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... If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal (PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. of the JTAG interface without COP connector. Freescale Semiconductor 10 kΩ HRESET ...
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... HRESET SRESET Figure 52. TRST Wiring for Boards without COP Connector 86 PORESET HRESET 10 kΩ VDD_IO 10 kΩ VDD_IO SRESET TRST 10 kΩ VDD_IO JTAG_TMS 10 kΩ VDD_IO TCK 10 kΩ VDD_IO TDI CKSTP_OUT TDO MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
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... This section details package parameters and dimensions. The MPC5125 is available in a thermally enhanced plastic ball grid array (TEPBGA). Section 6.1, “Package TEPBGA. 6.1 Package Parameters Package outline Interconnects Pitch Module height (typical) Solder balls Ball diameter (typical) Freescale Semiconductor Parameters,” and Section 6.2, “Mechanical Table 50. TEPBGA Parameters × 324 1.00 mm 2.25 mm 96.5 Sn/3.5Ag (VN package) 0.6 mm MPC5125 Microcontroller Data Sheet, Rev ...
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... Package Information 6.2 Mechanical Dimensions Figure 3 shows the mechanical dimensions and bottom surface nomenclature of the MPC5125 324 TEPBGA package. Figure 53. Mechanical Drawing of MPC5125 PBGA ( MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Figure 54. Mechanical Drawing of MPC5125 PBGA ( Freescale Semiconductor MPC5125 Microcontroller Data Sheet, Rev. 3 Package Information 89 ...
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... Package Information Figure 55. Mechanical Drawing of MPC5125 PBGA ( MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
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... October 2008 Initial public release, NDA required, Advance Information. 2 October 2009 Public release, Technical Data. 3 November 2009 Public release, Technical Data. Freescale Semiconductor Table 51. Revision History Description — Updated specifications according to characterized data. — Updated Table 1, orderable part numbers. — Updated Table 2, pin multiplexing ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...