MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 503

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This means the system programmer must choose SCL Period, SDA Hold, SCL Hold of START, and SCL
Hold of STOP from
In this case, the simplest strategy for the system programmer to use is:
Likewise, for fast mode I
That means the system programmer must choose SCL Period, SDA hold, SCL hold of START, and SCL
hold of STOP from
Freescale Semiconductor
(0.0003) × [SCL (in kHz)] × (SCL Period) ≤ SDA Hold ≤ (0.00345) × [SCL (in kHz)] × (SCL Period) Eqn. 19-6
1. Identify all rows of
2. Calculate the SCL associated with these rows according to
3. Find the subset of those rows associated with the acceptable I
4. Choose the preferred FDR setting from among the subset that meets
5. Check that the preferred FDR setting also satisfies
and
and
and
rows limits the choices of SCL allowed for this particular IPS clock.
are acceptable (fast enough or slow enough) for the system.
satisfies criteria in
Equation
does. If not, choose a different FDR setting that meets
Equation
and
and
and
19-6.
19-7, and
SCL Hold of START ≥ (0.004) × [SCL (in kHz)] × (SCL Period)
SCL Hold of STOP ≥ (0.004) × [SCL (in kHz)] × (SCL Period)
Table 19-6
Table 19-6
(SCL Period) ≥ (1/400,000) × [IPS clock speed (in Hz)]
SCL Period) ≥ (1/100,000) × [IPS clock speed (in Hz)]
2
C, it must also meet the fast-mode I
Equation
Equation
Table 19-6
MPC5125 Microcontroller Reference Manual, Rev. 2
(0.3 us ≤ SDA Hold Time ≤ 0.9 µs)
to satisfy
to satisfy
(SCL Hold of START ≥ 0.6 µs)
(SCL Hold of STOP ≥ 0.6 µs)
19-6.
19-8.
where SCL period satisfies criteria in
(SCL ≤ 400 kHz)
Equation 19-9
Equation 19-5
through
through
Equation 19-7
2
Equation
C bus specification.
Equation
Equation
Equation 19-1
2
C clock speeds such that SDA hold
19-5,
and
19-12:
19-8.
Equation 19-5
Equation
Equation
Equation
and decide which speeds
Inter-Integrated Circuit (I
19-5. This set of
19-8. Usually, it
19-6,
and
Eqn. 19-10
Eqn. 19-11
Eqn. 19-12
Eqn. 19-13
Eqn. 19-5
Eqn. 19-7
Eqn. 19-8
Eqn. 19-9
19-11
2
C)