MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 859

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.2.4.11 Master Interface Data Burst Size (USB_BURSTSIZE) Register
The Master Interface Data Burst Size (USB_BURSTSIZE) register controls and dynamically changes the
burst size used during data movement on the initiator (master) interface. This register is not defined in the
EHCI specification.
Freescale Semiconductor
Address: Base + 0x15C
Address: Base + 0x160
Reset
Reset
Reset
Reset
Figure 32-24. Host Controller Embedded TT Asynchronous Buffer Status (USB_TTCTRL) Register
TTHA
Field
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
0
0
0
(Non-EHCI)
Internal TT Hub Address Representation. Default is 0 (read/write). This field matches against the hub address
field in QH and siTD to determine if the packet is routed to the internal TT for directly attached FS/LS devices.
If the hub address in the QH or siTD does not match this address, the packet is broadcast on the high speed
ports destined for a downstream high speed hub with the address in the QH/siTD.
Figure 32-25. Master Interface Data Burst Size (USB_BURSTSIZE) Register
17
17
0
0
0
0
0
0
1
1
18
18
0
0
0
0
0
0
2
2
TXPBURST
19
19
0
0
0
0
0
1
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-25. USB_TTCTRL field descriptions
TTHA
20
20
4
0
0
0
4
0
0
0
21
21
0
0
0
0
0
0
5
5
22
22
0
0
0
0
0
0
6
6
23
23
0
0
0
0
0
0
7
7
Description
24
24
8
0
0
0
0
8
0
0
0
25
25
9
0
0
0
0
9
0
0
0
Universal Serial Bus Interface with On-The-Go
10
26
10
26
0
0
0
0
0
0
0
RXPBURST
11
27
11
27
0
0
0
0
0
0
1
12
28
12
28
0
0
0
0
0
0
0
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
0
32-31
15
31
15
31
0
0
0
0
0
0
0