MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 452

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
MPC5125YVN400
Manufacturer:
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Integrated Programmable Interrupt Controller (IPIC)
The interrupt controller provides the ability to mask each interrupt source. Multiple events within GPIO
or SBA peripheral event, are also maskable.
When the IPIC receives an internal or external interrupt, its configuration register is checked to determine
if it should be serviced as a normal external interrupt by the processor core (through the int signal). As a
third alternative, if the incoming interrupt has been configured as a critical or system management
interrupt, the IPIC completes the processing of the interrupt by asserting cint or smi to the core. The
assertion of the cint or smi signal to the core causes the interrupt to be serviced as a critical or a system
management interrupt, respectively.
18.1.1
The interrupt controller provides interrupt management responsible for receiving hardware-generated
interrupts from different sources (both internal and external). It also prioritizes and delivers the interrupts
to the CPU for servicing.
18.1.2
The IPIC unit implements the following features:
18.1.3
The IPIC unit can operate in the core enable or core disable mode.
18-4
Fifty-seven internal interrupts — on-chip interrupt signals sources are DDR, LPC, NFC, DMA,
FEC, PSC, FIFOC, USB, CSB arbiter, CAN, BDLC, DIU, SDHC, RTC, I
IIM and PMC.
One external and three internal non-maskable machine check exceptions. Off-chip interrupt signal
source is IRQ0. On-chip MCP interrupt signals sources are software watchdog timer
(WDT),TEMP and system bus arbiter (SBA)
Supports two external and internal discrete vectorized interrupt sources
Supports one external and three internal machine check processor (MCP) interrupt sources
Programmable highest priority request (can be programmed to support a critical (cint) or system
management (smi) interrupt type)
Two programmable priority mixed groups of four on-chip and four external interrupt signals with
two priority schemes for each group: grouped and spread
Four programmable priority internal groups of eight on-chip interrupt signals with two priority
schemes for each group: grouped and spread
Two highest priority interrupts from each group can be programmed to support a critical (cint) or
system management (smi) interrupt type
External and internal interrupts directed to host processor
Unique vector number for each interrupt source
Overview
Features
Modes of Operation
MPC5125 Microcontroller Reference Manual, Rev. 2
2
C, GPIO, GTM, TEMP,
Freescale Semiconductor

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