MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 187

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

an error occurs or the user sets the TEOD bit. For an illustration of the steps described below, refer to
Figure
Freescale Semiconductor
1. Load the IFR byte into the BDLC data register.
2. Set the TSIFR bit.
3. If necessary, set the TEOD bit.
6-23.
As with the Type 1 IFR, the user begins initiation of a Type 2 IFR by loading the desired IFR byte
into the BDLC Data Register. If a byte has already been written into the BDLC Data Register for
transmission as a new message, the user can simply write the IFR byte to the BDLC Data Register,
replacing the previously written byte. This must be done before the first EOD symbol is received.
The second step necessary for transmitting a Type 2 IFR is to set the TSIFR bit in BDLC Control
Register 2. Setting this bit directs the BDLC module to attempt to transmit the byte in the BDLC
Data Register as an IFR until it is successful. If the byte is transmitted successfully or if an error or
loss of arbitration occurs, TSIFR is cleared and no further transmit attempts are made.
The third step in transmitting a Type 2 IFR is only necessary if the user wishes to halt the
transmission attempts. This may be necessary if the BDLC module’s attempt to transmit the byte
loaded into the BDLC Data Register continually loses arbitration, and the overall message length
approaches the 12-byte limit as defined in SAE J1850.
If it becomes necessary to halt the IFR transmission attempts, the user simply sets the TEOD bit in
BDLC Control Register 2. If the BDLC module is between transmission attempts, it makes one
more attempt to transmit the IFR byte. If it is transmitting the byte when TEOD is set, the BDLC
module continues the transmission until it is successful or it loses arbitration to another transmitter.
At this point, it then discards the byte and make no more transmit attempts.
When transmitting a Type 2 IFR, the user should monitor the number of IFR
bytes received to ensure that the overall message length does not exceed the
12-byte limit for the length of SAE J1850 messages. The user should set the
TEOD bit when the 11th byte is received, which prevents the 12-byte limit
from being exceeded.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Byte Data Link Controller (BDLC)
6-51