MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 967

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If software has budgeted the schedule of this data stream with a frame wrap case, it must initialize the siTD
[Back Pointer] field to reference a valid siTD and have the T bit in the siTD [Back Pointer] field cleared.
Otherwise, software must set the T bit in siTD [Back Pointer]. The host controller's rules for interpreting
when to use the siTD [Back Pointer] field are listed below. These rules apply only when the siTD's active
bit is a one and the SplitXState is Do Complete Split.
When either of these conditions apply, the host controller must use the transaction state from siTD
To access siTD
The host controller must save the entire state from siTD
accommodate for case 2b processing. The host controller must not recursively walk the list of siTD [Back
Pointers].
If siTD
as described above. If these criteria to execute a complete-split are met, the host controller executes the
complete split and evaluates the results as described above. The transaction state (see
siTD
of siTD
pointer to the next schedule item. No updates to siTD
If siTD
active bit and set the missed micro-frame status bit and the resultant status is written back to memory.
If siTD
siTD
complete-split transaction cleared it), the host controller returns to the context of siTD
SplitXState to Do Start Split. The host controller then determines whether the case 2b start split boundary
condition exists (that is, if cMicroframeBit is 1 and siTD
controller immediately executes a start-split transaction and appropriately advances the transaction state
of siTD
controller simply follows siTD
the split-transaction of siTD
siTD
This scheduling combination is not supported and the behavior of the host controller is undefined.
32.6.11.3.4 Split Transaction for Isochronous - Processing Examples
There is an important difference between how the hardware/software manages the isochronous split
transaction state machine and how it manages the asynchronous and interrupt split transaction state
machines. The asynchronous and interrupt split transaction state machines are encapsulated within a single
queue head. The progress of the data stream depends on the progress of each split transaction. In some
respects, the split-transaction state machine is sequenced using the execute transaction queue head
traversal state machine.
Isochronous is a pure time-oriented transaction/data stream. The interface data structures are optimized to
efficiently describe transactions that need to occur at specific times. The isochronous split-transaction state
Freescale Semiconductor
•
•
X-1
X
X
’s back pointer, it transitioned to zero as a result of a detected error, or the results of siTD
. Software should not initialize an siTD with C-mask bits 0 and 1 set and an S-mask with bit 0 set.
X-1
X-1
X-1
When cMicroFrameBit is a 0x1 and the siTD
If cMicroFrameBit is a 0x2 and siTDX[S-mask[0]] is zero
X-1
X
is appropriately advanced based on the results and written back to memory. If the resultant state
, then follows siTD
’s Active bit is cleared, (because it was cleared when the host controller first visited siTD
’s active bit is a one, the host controller returns to the context of siTD
is active (Active bit is set and SplitXStat is Do Complete Split), Test A and Test B are applied
is active (Active bit is set and SplitXStat is Do Start Split), the host controller must clear the
X-1
, the host controller reads on-chip the siTD referenced from siTD
X-1
X
[Next Pointer] to the next schedule item. If the criterion is not met, the host
MPC5125 Microcontroller Reference Manual, Rev. 2
X
has its active bit cleared when the host controller returns to the context of
[Next Pointer] to the next schedule item. In the case of a 2b boundary case,
X
X
[Back Pointer] T-bit is zero, or
X
are necessary.
X
[S-mask[0]] is 1). If this criterion is met, the host
while processing siTD
Universal Serial Bus Interface with On-The-Go
X
X-1
and follows its next
X
. This is to
X
[Back Pointer].
Table
and transitions its
32-79) of
X-1
X-1
X-1
's
32-139
.
via