MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 928

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
In summary, system software enables the counter by setting the reload field (RL) to a non-zero value. The
host controller may execute a transaction if NakCnt is non-zero. The host controller does not execute a
transaction if NakCnt is zero. The reload mechanism is described in detail in
Count Reload Control.”
When all queue heads in the Asynchronous Schedule either exhausts all transfers or all NakCnt's go to
zero, then the host controller detects an empty Asynchronous Schedule and idle schedule traversal
(seeSection 32.6.7.3, “Empty Asynchronous Schedule
Any time the host controller begins a new traversal of the Asynchronous Schedule, a Start Event is
assumed, see
occurs, the Nak Count reload procedure is enabled.
32.6.8.1
When the host controller reaches the Execute Transaction state for a queue head (meaning that it has an
active operational state), it checks to determine whether the NakCnt field should be reloaded from RL (see
Section 32.6.9.3, “Execute
reload or if the reload is not active, the host controller evaluates whether to execute the transaction.
The host controller must reload nak counters in queue heads
the reclamation list after an asynchronous schedule Start Event (see
Schedule Traversal: Start Event,”
have at most one queue head marked as the head
machine that satisfies the operational requirements of the host controller detecting the first pass through
the Asynchronous Schedule. This state machine is maintained internal to the host controller and is only
used to gate reloading of the nak counter during the queue head traversal state: Execute Transaction
(Figure
Figure
32-100
•
•
32-48) is set to zero.
Not Used. This mode is set when the RL field is zero. The host controller ignores the NakCnt field
for any execution of transactions through a queue head with an RL field of zero. Software must use
this selection for interrupt endpoints.
Nak Throttle Mode. This mode is selected when the RL field is non-zero. In this mode, the value
in the NakCnt field represents the maximum number of Nak or Nyet responses the host controller
tolerates on each endpoint. In this mode, the HC decrements the NakCnt field based on the
token/handshake criteria listed in Table 34. The host controller must reload NakCnt when the
endpoint successfully moves data (e.g., policy to reward device for moving data).
32-61). The host controller does not perform the nak counter reload operation if the RL field (see
Section 32.6.7.5, “Asynchronous Schedule Traversal: Start Event.”
NAK Count Reload Control
Complete Split
IN/PING
Token
Transaction”). If the answer is yes, then RL is copied into NakCnt. After the
OUT
Split
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-73. NAKCnt Field Adjustment Rules
for the definition of the Start Event). The Asynchronous Schedule should
Decrement NAKCnt
Decrement NAKCnt
Decrement NAKCnt
Handshake NAK
No Action
(Figure
Detection”).
32-52).
(Figure
Figure 32-60
Decrement NAKCnt
N/A, Protocol Error
N/A, Protocol Error
Handshake NYET
Section 32.6.7.5, “Asynchronous
No Action Start
32-48) during the first pass through
Section 32.6.8.1, “NAK
illustrates an example state
Every time a Start-Event
Freescale Semiconductor