MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 871

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
BSEIE
BSVIE
ASVIE
BSEIS
BSVIS
ASVIS
AVVIE
AVVIS
1msE
1msS
1msT
Field
DPIE
DPIS
DPS
IDIE
IDIS
Data Pulse Interrupt Enable.
0 Disable.
1 Enable.
1 millisecond timer Interrupt Enable.
0 Disable.
1 Enable.
B Session End Interrupt Enable.
0 Disable.
1 Enable.
B Session Valid Interrupt Enable.
0 Disable.
1 Enable.
A Session Valid Interrupt Enable.
0 Disable.
1 Enable.
A VBus Valid Interrupt Enable.
0 Disable.
1 Enable.
USB ID Interrupt Enable.
0 Disable.
1 Enable.
Data Pulse Interrupt Status. This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is
only detected when USB_USBMODE[CM] equals Host (11) and PORTSC0[PP] equals Off (0).
Software must write a 1 to clear this bit.
1 millisecond timer Interrupt Status. This bit is set once every millisecond.
Software must write a 1 to clear this bit.
B Session End Interrupt Status. This bit is set when VBus has fallen below the B session end threshold.
Software must write a 1 to clear this bit.
B Session Valid Interrupt Status. This bit is set when VBus has risen above or fallen below the B session valid
threshold (0.8 VDC).
Software must write a 1 to clear this bit.
A Session Valid Interrupt Status. This bit is set when VBus has risen above or fallen below the A session valid
threshold (0.8 VDC).
Software must write a 1 to clear this bit.
A VBus Valid Interrupt Status. This bit is set when VBus has risen above or fallen below the VBus valid
threshold (4.4 VDC) on an A device.
Software must write a 1 to clear this bit.
USB ID Interrupt Status. This bit is set when a change on the ID input is detected.
Software must write a 1 to clear this bit.
Data Bus Pulsing Status.
0 No pulsing on port.
1 Pulsing detected on port.
1 millisecond timer toggle. This bit toggles once per millisecond.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-33. USB_OTGSC field descriptions
Description
Universal Serial Bus Interface with On-The-Go
32-43