MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 1000

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.8.9
The interrupt service routine must consider there are high-frequency, low-frequency, and error operations
to order accordingly.
32.8.9.1
High frequency interrupts in particular should be managed in the order below. The most important of these
is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible.
1
32.8.9.2
The low-frequency events include the following interrupts. These interrupts can be managed in any order
because they don't occur often in comparison to the high-frequency interrupts.
32.8.9.3
Error interrupts are least frequent and should be placed last in the interrupt service routine.
32-172
Overflow
ISO Packet Error
ISO Fulfillment Error
Port Change
Sleep Enable (Suspend)
Reset Received
Execution
It is likely that multiple interrupts to stack up on any call to the interrupt service routine and during the interrupt service routine.
Order
1a
1b
2
Interrupt
Servicing Interrupts
USB Interrupt
ENDPTSETUPSTATUS
USB Interrupt
ENDPTCOMPLETE
SOF Interrupt
High-Frequency Interrupts
Low-Frequency Interrupts
Error Interrupts
Interrupt
Number of bytes received exceeded max. packet size or total buffer length.
CRC Error on received ISO packet. Contents not guaranteed to be correct.
Host failed to complete the number of packets defined in the dQH mult field within the given
(micro)frame. For scheduled data delivery, DCD may need to readjust the data queue because a
fulfillment error causes device controller to cease data transfers on the pipe for one (micro)frame.
During dead (micro)frame, device controller reports error on the pipe and primes for the next frame.
1
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-100. Low Frequency Interrupt Events
Change software state information.
Change software state information. Low power handling as necessary.
Change software state information. Abort pending transfers.
Table 32-99. Interrupt Handling Order
Copy contents of setup buffer and acknowledge setup packet (as indicated in
section Managing Queue Heads). Process setup packet according to USB 2.0
Chapter 9 or application specific protocol.
Manages completion of dTD as indicated in section Managing Queue Heads.
Action as deemed necessary by application. This interrupt may not have a use in
all applications.
Table 32-98. Error Descriptions
Action
Action
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