MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 438

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IIM/Fusebox
17.3.1
All registers are 8-bit wide, but addressable on 32-bit boundaries. Only the least significant 8 bits (the
usable bits) of each register are shown in the following diagrams. The top most significant bits always read
as 0 and writes to them are ignored.
1
2
3
17.3.2
This section contains detailed descriptions of the IIM registers.
17.3.2.1
Figure 17-1
17-2
(0xFF40_B000)
0xC04–0xC7F
0x02C–0x03B
0xC80–0xFFF
0x040–0xBFF
0x020–0x027
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
Offset from
IIM_BASE
0x00C
0x01C
0x03C
0xC00
0x000
0x004
0x008
0x010
0x014
0x018
0x028
Memory Map
Register Descriptions
shows the bits in the Status (IIM_STAT) register.
Status (IIM_STAT) Register
1
IIM_STAT—Status register
IIM_STATM—Status IRQ Mask register
IIM_ERR—Module Errors register
IIM_FCTL—Fuse Control register
IIM_UA—Upper Address register
IIM_LA—Lower Address register
Reserved
IIM_PREG_P—Program Protection register
Reserved
Reserved
Reserved
IIM_EMASK—Error IRQ Mask register
IIM_SDAT—Explicit Sense Data register
IIM_DIVIDE—Divide Factor register
IIM_FBAC1—Fuse Bank 1 Protection Register
IIM_FB1W1—Fuse Bank 1 Data (available for user)
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 17-1
Register
Table 17-1. IIM memory map
shows the IIM memory map.
Table 17-2
Chapter 2, “System Configuration and Memory
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
describes the bit fields.
2
0x0000_00UU
0x0000_00UU
0x0000_000U
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0030
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0042
Freescale Semiconductor
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