MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 126

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks and Low-Power Modes
5.3.1.18
The DIU Clock Config Register (DCCR), shown in
Systems Bus (CSB) cycles delay added to the pixel clock to pad compare to pixel clock to DIU block, and
whether the DIU pixel clock is inverted.
5-26
Address: Base + 0x40
MCLK_0_SRC
MCLK_1_SRC
MCLK9_EN
MCLK_DIV
Reset
Reset
PSC9_
PSC9_
PSC9_
Field
W
W
R
R
PSC9_MCLK
16
1
_0_SRC
0
0
DIU Clock Config Register (DCCR)
MCLK_DIV Divider Ratio
Note: The maximum supported frequency for f
A value of 0x0000 bypasses the divider.
Note: This value can only be changed when the value of MCLK_EN equals 0.
PSC9 Divider Enable
0 PSC9 divider is disabled.
1 PSC9 divider is enabled.
PSC MCLK Divider Source
00 From SYS_CLK.
01 From REF_CLK.
10 From PSC_MCLK_IN.
11 From CAN_CLK_IN.
PSC MCLK Source
0 MCLK_DIV.
1 Reserved.
17
1
0
1
f
mclk_out
18
1
0
0
2
= f
Figure 5-22. PSC9 Clock Control Register 9 (P9CCR)
mclk_src
19
1
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
/ (MCLK_DIV + 1)
Table 5-22. P9CCR field descriptions
20
4
1
0
0
21
Table 5-23
1
0
0
5
PSC9_MCLK_DIV
22
1
0
0
6
Figure
defines the bit fields of DCCR.
23
1
0
0
7
mclk_out
Description
MCLK_
PSC9_
1_SRC
24
8
1
0
5-23, configures the number of Coherent
is the IP Bus frequency.
25
9
1
0
0
10
26
1
0
0
11
27
1
0
0
12
28
1
0
0
Freescale Semiconductor
Access: User read/write
13
29
1
0
0
14
30
1
0
0
MCLK
9_EN
15
31
0
0
0