MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 242

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
9.2.1.14
The DMA Error High (DMAERRH) and DMA Error Low (DMAERRL) registers provide a bit map for
the implemented 64 channels signaling the presence of an error for each channel. DMAERRH supports
channels 63–32, while DMAERRL covers channels 31–00. The DMA_ENGINE signals the occurrence of
an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by
the contents of the DMAEEI register, then logically summed across groups of 16, 32, and 64 channels to
form several group error interrupt requests routed to the platform’s interrupt controller. During the
execution of the interrupt service routine associated with any DMA errors, it is software’s responsibility
to clear the appropriate bit, negating the error interrupt request. Typically, a write to the DMACERR
register in the interrupt service routine is used for this purpose. Recall the normal DMA channel
9-22
Address: Base + 0x0020
Address: Base + 0x0024
Reset
Reset
Reset
Reset
Field
INTn
W
W
W
W
R INT
R INT
R INT
R INT
63
47
31
15
16
16
0
0
0
0
0
0
DMA Error (DMAERRH, DMAERRL)
DMA Interrupt Request n
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.
INT
INT
INT
INT
62
46
30
14
17
17
0
0
0
0
1
1
INT
INT
INT
INT
Figure 9-15. DMA Interrupt Request Register High (DMAINTH)
61
45
29
13
Figure 9-16. DMA Interrupt Request Register Low (DMAINTL)
18
18
0
0
0
0
2
2
Table 9-16. DMAINTH and DMAINTL field descriptions
INT
INT
INT
INT
60
44
28
12
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
INT
INT
INT
INT
59
43
27
11
20
20
4
0
0
4
0
0
INT
INT
INT
INT
58
42
26
10
21
21
0
0
0
0
5
5
INT
INT
INT
INT
57
41
25
09
22
22
0
0
0
0
6
6
INT
INT
INT
INT
56
40
24
08
23
23
0
0
0
0
7
7
Description
INT
INT
INT
INT
55
39
23
07
24
24
8
0
0
8
0
0
INT
INT
INT
INT
54
38
22
06
25
25
9
0
0
9
0
0
INT
INT
INT
INT
53
37
21
05
10
26
10
26
0
0
0
0
INT
INT
INT
INT
52
36
20
04
11
27
11
27
0
0
0
0
INT
INT
INT
INT
51
35
19
03
12
28
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
INT
INT
INT
INT
50
34
18
02
13
29
13
29
0
0
0
0
INT
INT
INT
INT
49
33
17
01
14
30
14
30
0
0
0
0
INT
INT
INT
INT
48
32
16
00
15
31
15
31
0
0
0
0