MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 993

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.8.5.3
Isochronous endpoints are used for real-time scheduled delivery of data and their operational model is
significantly different than the host throttled bulk, interrupt, and control data pipes. Real time delivery by
the USB controller is accomplished by:
The USB controller in host mode uses the periodic frame list to schedule data exchanges to isochronous
endpoints. The operational model for device mode does not use such a data structure. Instead, the same
dTD used for control/bulk/interrupt endpoints is also for isochronous endpoints. The difference is in the
handling of the dTD.
The first difference between bulk and ISO-endpoints is priming an ISO-endpoint is a delayed operation
such that an endpoint becomes primed only after a SOF is received. After the DCD writes the prime bit,
the prime bit is cleared as usual to indicate to software the device controller completed a priming the dTD
for transfer. Internal to the design, the device controller hardware masks that prime start until the next
frame boundary. This behavior is hidden from the DCD, but occurs so the device controller can match the
dTD to a specific (micro)frame.
Another difference with isochronous endpoints is the transaction must wholly complete in a (micro)frame.
After an ISO transaction is started in a (micro)frame, it retires the corresponding dTD when MULT
transactions occur or the device controller finds a fulfillment condition.
The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment
error occurs, the frame after the transfer failed to complete wholly, the device controller forces retirement
of the ISO-dTD and move to the next ISO-dTD.
Fulfillment errors are caused only by partially completed packets. If no activity occurs to a primed
ISO-dTD, the transaction stays primed indefinitely. Thus, software must discard transmit ISO-dTDs that
pile up from a failure of the host to move the data.
The last difference with ISO packets is in the data level error handling. When a CRC error occurs on a
received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is noted
by setting the transaction error bit and the data is stored as usual for the application software to sort out.
Freescale Semiconductor
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Exactly MULT Packets per (micro) Frame are transmitted/received.
NAK responses are not used. Instead, zero length packets are sent in response to an IN request to
an unprimed endpoint. For unprimed RX endpoints, the response to an OUT transaction is to ignore
the packet within the device controller.
Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If the
ISO-dTD remains active after that frame, the ISO-dTD is held ready until executed or canceled by
the DCD.
TX Packet Retired
— MULT counter reaches zero.
— Fulfillment Error [Transaction Error bit is set]
Isochronous Endpoint Operational Model
MULT is a two-bit field in the device Queue Head. The variable length
packet protocol is not used on isochronous endpoints.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Universal Serial Bus Interface with On-The-Go
32-165