MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 481

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.2.1.20 System Error Force Register (IPIC_SERFR)
Each bit in the System Error Force Register (IPIC_SERFR), shown in
external MCP source. When a bit is set, the interrupt controller generates the corresponding MCP interrupt
(sets the corresponding IPIC_SERSR bit).
The IPIC_SERFR can be read by the user at any time.
1
18.2.1.21 System Critical Interrupt Vector Register (IPIC_SCVCR)
The System Critical Interrupt Vector Register (IPIC_SCVCR), shown in
code
Freescale Semiconductor
Address: Base + 0x5C
1. This bit is valid only if the IRQ0 signal is configured as an external MCP interrupt (IPIC_SEMSR[SIRQ0] = 1)
TEMP 125C
Reset
Reset
TEST
Field
IRQ0
IRQ1
Field
IRQ0
WDT
(Table
SBA
W
W
R
R
IRQ0
16
0
0
0
0
18-26) representing the unmasked critical interrupt (cint) source of the highest priority level.
1
Each bit corresponds to an external interrupt source. Force an interrupt by setting the IPIC_SIFCRx bit. An
interrupt can be enabled by setting the corresponding IPIC_SIFCRx bit.
Note: IPIC_SIFCRx bit positions are not changed according to their relative priority.
Each bit corresponds to an external MCP source. The user can force an MCP by setting the IPIC_SERFR bit.
Note: IPIC_SERFR bit positions are not affected by their relative priority.
WDT
17
0
0
0
1
SBA
18
0
0
0
2
Figure 18-24. System Error Force Register (IPIC_SERFR)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-24. IPIC_SEFCR field descriptions
Table 18-25. IPIC_SERFR field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
TEST
24
8
0
0
0
TEMP
125C
Integrated Programmable Interrupt Controller (IPIC)
25
9
0
0
0
Figure
10
26
0
0
0
0
Figure
11
27
0
0
0
0
18-24, corresponds to an
18-25, contains a 7-bit
12
28
0
0
0
0
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
18-33
15
31
0
0
0
0