MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 977

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.7.1.2
The seven 32-bit words in the overlay area represent a transaction working space for the device controller.
The general operational model is that the device controller can detect whether the overlay area contains a
description of an active transfer. If it does not contain an active transfer, it does not read the associated
endpoint.
After an endpoint is readied, the dTD is copied into this queue head overlay area by the device controller.
Until a transfer is expired, software must not write the queue head overlay area or the associated transfer
descriptor. When the transfer is complete, the device controller writes the results back to the original
transfer descriptor and advances the queue.
See dTD for a description of the overlay fields.
32.7.1.3
The device controller uses the current dTD pointer to locate the transfer in progress. This word is for
hardware use only, and DCD software should not modified it.
Freescale Semiconductor
31:30
28:27
26:16
14:0
31:5
Bit
Bit
4:0
29
15
Transfer Overlay
Current dTD Pointer
Mult. This field indicates the number of packets executed per transaction description as given by the following:
00 Execute n transactions as demonstrated by the USB variable length packet protocol where n is computed
01 Execute 1 Transaction
10 Execute 2 Transactions
11 Execute 3 Transactions
Note: Non-ISO endpoints must set Mult equal to 00.
Note: ISO endpoints must set Mult equal to 01, 10, or 11 as needed.
Zero Length Termination Select. This bit indicates when a zero length packet terminates transfers where total
transfer length is a multiple. This bit is not relevant for isochronous transfers.
0 Enable zero length packet to terminate transfers equal to a multiple of the maximum packet length. (default).
1 Disable the zero length packet on transfers equal in length to a multiple maximum packet length.
Reserved. These bit reserved for future use and should be set to 0.
Maximum Packet Length. This directly corresponds to the maximum packet size of the associated endpoint
(wMaxPacketSize). The maximum value this field may contain is 0x400 (1024).
Interrupt On Setup (IOS). This bit is used on control type endpoints to indicate if USBINT is set in response to
a setup being received.
Reserved. Bits reserved for future use and should be set to 0.
Current dTD. This field is a pointer to the dTD that is represented in the transfer overlay area. This field is
modified by the device controller to the next dTD pointer during endpoint priming or queue advance.
Reserved. Bit reserved for future use and should be set to zero.
using the maximum packet length (dQH) and the total bytes field (dTD)
Table 32-83. Endpoint Capabilities/Characteristics
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-84. Current dTD Pointer
Description
Description
Universal Serial Bus Interface with On-The-Go
32-149