MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 880

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32-52
Address: Base + 0x1C4 (USB_ENDPTCTRL1)
Reset
Reset
Field
TXE
TXR
TXT
TXD
TXS
TXI
W
W
R
R
Base + 0x1C8 (USB_ENDPTCTRL2)
Base + 0x1CC (USB_ENDPTCTRL3)
16
0
0
0
0
0
TX Endpoint Enable.
0 Disabled.
1 Enabled.
TX Data Toggle Reset. When a configuration event is received for this endpoint, software must write a one to
this bit to synchronize the data PIDs between the host and device.
TX Data Toggle Inhibit. This bit is used only for test and should always be written as zero. Writing a one to this
bit causes this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
0 PID Sequencing Enabled.
1 PID Sequencing Disabled.
TX Endpoint type.
00 Control.
01 Isochronous.
10 Bulk.
11 Interrupt.
TX Endpoint Data Source. This bit should always be written as 0, which selects the Dual Port Memory/DMA
Engine as the source.
TX Endpoint Stall. This bit is set automatically upon receipt of a setup request if this endpoint is not configured
as a control endpoint. It is cleared automatically upon receipt of a setup request if this endpoint is configured
as a control endpoint.
Software can write a 1 to this bit to force the endpoint to return a stall handshake to the host. It continues
returning stall until this bit is cleared by software or automatically cleared as above.
Software can write a 1 to this bit to force the endpoint to return a stall handshake to the Host. This control
continues to stall until this bit is either cleared by software or automatically cleared as above for control
endpoints.
Note: [Control endpoint types only] There is a slight delay (50 clocks max.) between the associated bit in the
0 Endpoint OK.
1 Endpoint Stalled.
17
0
0
0
0
1
USB_ENDPTSETUPSTAT register being cleared and hardware continuing to clear this bit. In most
systems, it is unlikely the DCD software observes this delay. However, should the DCD observe that the
stall bit is not set after writing a 1 to it, follow this procedure: continually write this stall bit until it is set
or until a new setup has been received by checking the associated bit in the USB_ENDPTSETUPSTAT
register.
Figure 32-40. Endpoint Control Register n (USB_ENDPTCTRLn)
18
0
0
0
0
2
Table 32-41. USB_ENDPTCTRLn field descriptions
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
RXE
TXE
24
8
0
0
RXR
TXR
25
9
0
0
RXI
TXI
10
26
0
0
11
27
0
0
0
0
12
28
0
0
Freescale Semiconductor
Access: User read/write
RXT
TXT
13
29
0
0
TXD
RXD
14
30
0
0
RXS
TXS
15
31
0
0