MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 970

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.13 Port Test Modes
EHCI host controllers implement the port test modes Test J_State, Test K_State, Test_Packet, Test
Force_Enable, and Test SE0_NAK as described in the USB Specification Revision 2.0. The required, port
test sequence is (assuming the CF bit in the USB_CONFIGFLAG register is set):
32.6.14 Interrupts
The EHCI host controller hardware provides interrupt capability based on a number of sources. There are
several general groups of interrupt sources:
All transaction-based sources are maskable through the host controller's interrupt enable register
(USB_USBINTR). Additionally, individual transfer descriptors can be marked to generate an interrupt on
completion. This section describes each interrupt source and the processing that occurs in response to the
interrupt.
During normal operation, interrupts may be immediate or deferred until the next interrupt threshold occurs.
The interrupt threshold is a tunable parameter via the interrupt threshold control field in the
USB_USBCMD register. The value of this register controls when the host controller generates an interrupt
on behalf of normal transaction execution. When a transaction completes during an interrupt interval
period, the interrupt signaling the completion of the transfer does not occur until the interrupt threshold
occurs. For example, the default value is eight micro-frames. This means that the host controller does not
generate interrupts any more frequently than once every eight micro-frames.
Section 32.6.14.2.4, “Host System Error,”
If an interrupt is scheduled to be generated for the current interrupt threshold interval, the interrupt is not
signaled until after the status for the last complete transaction in the interval has been written back to
system memory. This may result in the interrupt not being signaled until the next interrupt threshold.
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Disable the periodic and asynchronous schedules by clearing the asynchronous schedule enable
and periodic schedule enable bits in the USB_USBCMD register.
Place all enabled root ports into the suspended state by setting the suspend bit in each appropriate
USB_PORTSCn register.
Clear the run/stop bit in the USB_USBCMD register and wait for the HCHalted bit in the
USB_USBSTS register, to transition to a 1. An EHCI host controller implementation may
optionally allow port testing with the run/stop bit set. However, all host controllers must support
port testing with run/stop cleared and HCHalted set.
Set the port test control field in the port under test USB_PORTSCn register to the value
corresponding to the desired test mode. If the selected test is Test_Force_Enable, the run/stop bit
in the USB_USBCMD register must be transitioned back to one to enable transmission of SOFs
out of the port under test.
When the test is complete, system software must ensure the host controller is halted (HCHalted
bit = 1), it terminates and exits test mode by setting HCReset.
Interrupts as a result of executing transactions from the schedule (success and error conditions),
Host controller events (Port change events, etc.), and
Host controller error events
MPC5125 Microcontroller Reference Manual, Rev. 2
details the effects of a host system error.
Freescale Semiconductor