MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 668

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power Management Control Module (PMC)
24.2.2.3
24-4
Address: Base + 0x08
Reset
Reset
WDTO
INT1E
Field
Field
INT1
INT2
W
W
R
R
16
0
0
0
0
0
PMC Interrupt Mask Register (PMC_PMCMR)
Interrupt Event 1
0 Interrupt event 1 did not occur.
1 Interrupt event 1 condition occurred. This bit is asserted when the Power Architecture core is in nap or
Interrupt Event 2
0 Interrupt event 2 did not occur.
1 Interrupt event 2 condition occurred. This bit is asserted when the system is about to exit from the core
DDR Response Watchdog Time Out
0 DDR response watchdog time out did not occur
1 DDR response watchdog time out occurred. While entering deep sleep mode, or while entering nap, sleep
Interrupt 1 Enable
0 Interrupt is not generated when interrupt event 1 occurs.
1 Interrupt is generated when interrupt event 1 occurs.
17
0
0
0
0
1
sleep mode and another CSB master (i.e. JTAG or tester for MPC5125) initiates CSB transactions without
sending interrupt to the core in advance. If enabled an interrupt can be generated in this condition which
can be used to wake up the core from nap or sleep mode.
PLL change or PRE_DIV copy mode. Interrupt is generated in this condition which should be used to bring
the Power Architecture core back to the full operational mode. The interrupt is always sent in this condition
(i.e. non-maskable), but still needs to be enabled in the IPIC so that it reaches the e300 core.
or PRE_DIV copy mode if PMC_PMCCR[DDROFF] bit is set, PMC requests the DRAM controller to put
DDR into self-refresh mode before placing the e300 core in nap or sleep mode. If no response is received
from the DRAM controller in approximately 1 mS, the process is terminated and restarted again until
software terminates it. The WDTO bit is set in this scenario for debug purpose. Interrupt is not generated.
18
0
0
0
0
2
Figure 24-3. PMC Interrupt Mask Register (PMC_PMCMR)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 24-4. PMC_PMCMR field descriptions
Table 24-3. PMC_PMCER field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
INT1E
15
31
0
0
0