MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 966

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
If Test A succeeds, but Test B fails, it means one or more of the complete-splits have been skipped. The
host controller sets the missed micro-frame status bit and clears the active bit.
Complete-Split for Scheduling Boundary Cases 2a, 2b
Boundary cases 2a and 2b (INs only) (see
context of the previous siTD to finish the split transaction.
fields.
32-138
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data than was expected, or allowed for was actually received. This short packet event does not set
the USBINT status bit in the USB_USBSTS register to a one. The host controller does not detect
this condition.
NYET (and Last). On each NYET response, the host controller also checks to determine whether
this is the last complete-split for this split transaction. Last was defined in section periodic interrupt
- Do Complete Split. If it is the last complete-split (with a NYET response), the transfer state of
the siTD is not advanced (never received any data) and the Active bit is cleared. No bits are set in
the status field because this is essentially a skipped transaction. The transaction translator must
have responded to all the scheduled complete-splits with NYETs, meaning the start-split issued by
the host controller was not received. This result should be interpreted by system software as if the
transaction was completely skipped. The test for whether this is the last complete split can be
performed by XORing C-mask with C-prog-mask. A zero result indicates that all complete-splits
have been executed.
MDATA (and Last). See above description for testing for Last. This can only occur when there is
an error condition. There has been a babble condition on the full-speed link, which delayed the
completion of the full-speed transaction or software set up the S-mask and/or C-masks incorrectly.
The host controller must set the XactErr bit and clear the active bit.
NYET (and not Last). See above description for testing for Last. The complete-split transaction
received a NYET response from the transaction translator. Do not update any transfer state (except
for C-prog-mask) and stay in this state.
MDATA (and not Last). The transaction translator responds with an MDATA when it has partial
data for the split transaction. For example, the full-speed transaction data payload spans from
micro-frame X to X+1 and during micro-frame X, the transaction translator responds with an
MDATA and the data accumulated up to the end of micro-frame X. The host controller advances
the transfer state to reflect the number of bytes received.
Total Bytes To Transfer
P (page select)
Current Offset
TP (transaction position)
T-count (transaction count)
TP and T-count are only for host to device (OUT) endpoints.
Buffer State
Table 32-79. Summary siTD Split Transaction State
MPC5125 Microcontroller Reference Manual, Rev. 2
All bits in the status field
Figure
32-68) require the host controller use the transaction state
NOTE
Status
Table 32-79
C-prog-mask
Execution Progress
enumerates the transaction state
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