MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 200

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CPU e300 Core Power Architecture
Bursting is supported on the Coherent Systems Bus (CSB). Critical word first protocol is employed when
the e300c4 core attempts to fill its address and data caches. The ID values for the MPC5125 are shown in
Table
7.3
A complete specification for the e300c4 core implementation used on the module is obtained through a
collection of documentation.
The programming environments manual provides information about resources defined by the Power
Architecture architecture common to Power Architecture processors. Implementation variances relative to
Rev. 4 of the Programming Environments Manual are available in the e300 Core Reference Manual.
The e300 Power Architecture Core Family Reference Manual can be obtained from the Freescale
Literature Distribution center at http://www.freescale.com.
7.4
7.4.1
Two Power Architecture instructions are not supported by the module. These two instructions are eciwx
and ecowx. The execution of both instructions generates a TEA signal on the CSB. This causes a machine
check exception or a checkstop.
7.4.2
Enabling of the address or data parity error check by setting the HID0[EBA, EBD] bits generates a
machine check exception or a checkstop depending on the HID0[EMCP] bit.
7-2
•
•
7-1.
Power Architecture Microprocessor Family: The Programming Environments for 32-bit
Microprocessors, Rev. 2: MPCFPE32B/AD
e300 Power Architecture Core Family Reference Manual, Rev. 4
e300c4 Core Reference Manual
Unsupported e300c4 Core Features
Instructions
CSB Parity
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 7-1. ID Values for the MPC5125
MPC5125 SVR
JTAG ID Code
PVR
M01S Mask Set
0x0540_C01D
0x8086_2010
0x8019_0010
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