MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 249

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 9-26
Figure 9-27
Freescale Semiconductor
Address: Base + 0x1000 + (32 × n) + 0x000C
Address: Base + 0x1000 + (32 × n) + 0x0010
DADDR[31:0]
SLAST[31:0]
Reset
Reset
Reset
Reset
Field
Field
W
W
W
W
R
R
R
R
See
See
—
—
—
—
16
16
0
0
and
and
Table 9-1
Table 9-1
Last source address adjustment. Adjustment value added to the source address at the completion of the outer
major iteration count.
This value can be applied to restore the source address to the initial value, or adjust the address to reference
the next data structure.
Destination address. Memory address pointing to the destination data.
—
—
Table 9-26
—
—
Table 9-27
17
17
1
1
and
and
—
—
—
—
18
18
2
2
Table
Table
Table 9-25. TCDn Word 3 (TCDn.slast) field descriptions
define word 4 of the TCDn structure, the DADDR field.
define word 5 of the TCDn structure, the CITER and DOFF fields.
—
19
—
—
19
—
3
3
Figure 9-26. TCDn Word 4 (TCDn.DADDR) Field
9-21.
9-21.
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 9-25. TCDn Word 3 (TCDn.slast) Field
Table 9-26. TCDn Word 4 field descriptions
—
—
—
—
20
20
4
4
—
—
—
—
21
21
5
5
—
—
—
—
22
22
6
6
DADDR[31:16]
DADDR[15:00]
SLAST[31:16]
SLAST[15:00]
—
—
—
—
23
23
7
7
Description
Description
—
—
—
—
24
24
8
8
—
—
—
—
25
25
9
9
—
—
—
—
10
26
10
26
—
—
—
—
11
27
11
27
Direct Memory Access (DMA)
—
—
—
—
12
28
12
28
Access: User read/write
Access: User read/write
—
—
—
—
13
29
13
29
—
—
—
—
14
30
14
30
—
—
—
—
15
31
15
31
9-29