MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 465

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.2.1.7
The system internal interrupt group D priority register (IPIC_SIPRR_D), shown in
the priority between the I2C1, I2C2, I2C3, MSCAN1, MSCAN2, BDLC, GPT0, and GPT1 internal
interrupt signals.
Freescale Semiconductor
Address: Base + 0x1C
SYSC1P–
Reset
Reset
SYSC0P
SYSC7P
Field
W
W
R
R
16
0
1
0
Figure 18-9. System Internal Interrupt Group D Priority Register (IPIC_SIPRR_D)
System Internal Interrupt Group D Priority Register (IPIC_SIPRR_D)
SYSD0P
SYSD4P
SYSC0 Priority order. Defines which interrupt source asserts its request in the SYSC0 priority position. The
user should not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. The definition of SYSC0P is shown as follows:
000 GPT10 asserts its request in the SYSC0 position.
001 GPT11 asserts its request in the SYSC0 position.
010 SDHC2 asserts its request in the SYSC0 position.
011 FEC1 asserts its request in the SYSC0 position.
100 FEC2 asserts its request in the SYSC0 position.
101 NFC asserts its request in the SYSC0 position.
110 LPC asserts its request in the SYSC0 position.
111 SDHC1 asserts its request in the SYSC0 position.
Same as SYSC0P, but for SYSC1P–SYSC7P.
17
0
0
1
18
0
0
2
19
0
1
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-9. IPIC_SIPRR_C field descriptions
SYSD1P
SYSD5P
20
4
0
0
21
1
1
5
22
0
1
6
SYSD2P
SYSD6P
23
1
1
7
Description
24
8
0
0
Integrated Programmable Interrupt Controller (IPIC)
25
9
0
1
SYSD3P
SYSD7P
10
26
1
1
11
27
0
1
12
28
Figure
0
0
0
0
Access: User read/write
13
29
0
0
0
0
18-9, defines
14
30
0
0
0
0
18-17
15
31
0
0
0
0