MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 961

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If a transaction translator returns with the final data before all of the complete-splits have been executed,
the state of the transfer is advanced so the remaining complete-splits are not executed. An IN siTD is
retired based solely on the responses from the transaction translator to the complete-split transactions. This
means, for example, it is possible for a transaction translator to respond to a complete-split with an
MDATA PID. The number of bytes in the MDATA’s data payload could cause the siTD [total bytes to
transfer] field to decrement to zero. This response can occur, before all of the scheduled complete-splits
have been executed. In another interface such as data structures (for example, high-speed data streams
through queue heads), the transition of total bytes to transfer to zero signals the end of the transfer and
results in clearing the active bit. However, in this case, the result has not been delivered by the transaction
translator and the host must continue with the next complete-split transaction to extract the residual
transaction state. This scenario occurs because of the pipeline rules for a transaction translator. In
summary, the periodic pipeline rules require that on a micro-frame boundary, the transaction translator
holds the final two bytes received (if it has not seen an end of packet [EOP]) in the full-speed bus pipe
stage and gives the remaining bytes to the high-speed pipeline stage. At the micro-frame boundary, the
transaction translator could have received the entire packet (including both CRC bytes), but not received
the packet EOP. In the next micro-frame, the transaction translator responds with an MDATA and sends
all of the data bytes (with the two CRC bytes held in the full-speed pipeline stage). This could cause the
siTD to decrement it's total bytes to transfer field to zero, indicating it has received all expected data. The
host must continue to execute one more (scheduled) complete-split transactions to extract the results of the
full-speed transaction from the transaction translator (for example, the transaction translator may have
detected a CRC failure, and this result must be forwarded to the host).
If the host experiences hold-offs that cause the host controller to skip one or more (but not all) scheduled
split transactions for an isochronous OUT, the protocol to the transaction translator is not consistent and
the transaction translator detects and reacts to the problem. Likewise, for host hold-offs that cause the host
controller to skip one or more (but not all) scheduled split transactions for an isochronous IN, the
C-prog-mask is used by the host controller to detect errors. However, if the host experiences a hold-off that
causes it to skip all of an siTD, or an siTD expires during a host hold off (for example, a hold-off occurs
and the siTD is no longer reachable by the host controller for it to report the hold-off event), system
software must detect the siTDs have not been processed by the host controller (for example, state not
advanced) and report the appropriate error to the client driver.
32.6.11.3.3 Split Transaction Execution State Machine for Isochronous Transactions
In this section, all references to micro-frame are in the context of a micro-frame within an H-Frame.
If the active bit in the status byte is a zero, the host controller ignores the siTD and continues traversing
the periodic schedule. Otherwise, the host controller processes the siTD as specified below. A split
transaction state machine manages the split-transaction protocol sequence. The host controller uses the
fields defined in
plus the variable cMicroFrameBit defined in
Machine for Interrupt,”
the state machine for managing an siTD through an isochronous split transaction. Bold, dotted circles
Freescale Semiconductor
transaction. If the previous complete-splits have not been executed, it means one (or more) have
been skipped and data has potentially been lost. System software is required to initialize this field
to zero before setting an siTD's active bit to a one.
Section 32.6.11.3.2, “Tracking Split Transaction Progress for Isochronous Transfers,”
to track the progress of an isochronous split transaction.
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 32.6.11.2.4, “Split Transaction Execution State
Universal Serial Bus Interface with On-The-Go
Figure 32-70
illustrates
32-133