MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 589

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Freescale Semiconductor
The MSCAN must be in normal mode for this bit to become set.
See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.
The Power Architecture has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see
Section 22.3.2.6, “MSCAN Receiver Interrupt Enable Register
sleep mode is required.
The Power Architecture cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
The Power Architecture cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
To protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the
initialization mode is requested by the Power Architecture. Thus, the recommended procedure is to bring the MSCAN into sleep
mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
Not including WUPE, INITRQ, and SLPRQ.
TSTAT1 and TSTAT0 are not affected by initialization mode.
RSTAT1 and RSTAT0 are not affected by initialization mode.
INITRQ
SLPRQ
WUPE
Field
TIME
5,6
3
4
Timer Enable bit activates an internal 16-bit wide free running timer clocked by the bit-clock. If timer is enabled,
a 16-bit time stamp is assigned to each transmitted/received message within the active Tx/Rx buffer. As soon
as a message is acknowledged on CAN, the time stamp is written to the highest bytes (0x1C, 0x1D) in the
appropriate buffer (see
(all bits set to 0) when initialization mode is active.
0 Disable internal MSCAN timer.
1 Enable internal MSCAN timer.
Wake-Up Enable bit lets MSCAN restart when being locked in idle state during sleep mode and traffic on CAN
is detected (see
0 Wake-Up disabled. The MSCAN ignores traffic on CAN.
1 Wake-Up enabled.The MSCAN is able to restart.
Sleep Mode Request bit requests MSCAN enter sleep mode, an internal power saving mode (see
Section 22.4.8.1, “MSCAN Sleep
the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep
mode by setting SLPAK = 1 (see
active until SLPRQ is cleared by the Power Architecture or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running.The MSCAN functions normally.
1 Sleep Mode Request. The MSCAN locks in idle state.
Initialization Mode Request. When this bit is set by the Power Architecture, the MSCAN skips to initialization
mode (see
and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting
INITAK = 1
The following registers enter their hard reset state and restore their default values: CANCTL0
CANRIER
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the Power Architecture when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The
values of the error counters are not affected by initialization mode.
When this bit is cleared by the Power Architecture, the MSCAN restarts and then tries to synchronize to the
CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN
bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation.
1 MSCAN in initialization state.
9
Section 22.4.8.2, “MSCAN Initialization
, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
(Section 22.3.2.2, “MSCAN Control 1 Register
Table 22-4. CANCTL0 field descriptions (continued)
Section 22.4.8.1, “MSCAN Sleep
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 22.3.3, “Programmer’s Model of Message
Section 22.3.2.2, “MSCAN Control 1 Register
Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e.,
(CANRIER)”) is enabled, if the recovery mechanism from deep
Description
Mode”).
Mode”). Any ongoing transmission or reception is aborted
(CANCTL1)”).
Storage”). The internal timer is reset
(CANCTL1)”). Sleep mode is
7
, CANRFLG
MSCAN
22-11
8
,