MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 176

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.4.5.2.1
If a loss of arbitration (LOA) occurs while the BDLC module is transmitting onto the SAE J1850 bus, the
BDLC module immediately stops transmitting, and a LOA status is reflected in the BDLC_DLCBSVR
register. If the loss of arbitration has occurred on a byte boundary, an RDRF interrupt may also be pending
once the LOA interrupt is cleared.
When a loss of arbitration occurs, the J1850 message handling software should immediately switch into
the receive mode. If the TEOD bit was set, it is cleared automatically. If another attempt is to be made to
transmit the same message, the user must start the transmit sequence over from the beginning of the
message.
6.4.5.2.2
Similar to a loss of arbitration, if any error (except a CRC error) is detected on the SAE J1850 bus during
a transmission, the BDLC module stops transmitting immediately. The transmitted byte is discarded, and
the symbol invalid or out of range status is reflected in the BDLC_DLCBSVR register. As with the loss of
arbitration, if the TEOD bit was set, it is cleared automatically and any attempt to transmit the same
message has to start from the beginning.
If a CRC error occurs following a transmission, this is also reflected in the BDLC_DLCBSVR register.
However, since the CRC error is really a receive error based on the received CRC byte, at this point all
bytes of the message have been transmitted. Thus, software must determine whether another attempt
should be made to transmit the message in which the error occurred.
6.4.5.2.3
A transmitter underrun can occur when a TDRE interrupt is not serviced in a timely fashion. If the last byte
loaded into the BDLC Data Register is completely transmitted onto the network before the next byte is
loaded into the BDLC Data Register, a transmitter underrun occurs. If this does happen, the BDLC module
transmits two additional logic ones to ensure that the partial message transmitted onto the bus does not end
on a byte boundary. This is followed by an EOD and EOF symbol. The only indication to the CPU that an
underrun occurred is the Symbol Invalid or Out of Range error indicated in the BDLC_DLCBSVR
register. As with the other errors, software must determine whether another transmission attempt should
be made.
6.4.5.2.4
If an In-Frame Response (IFR) is received following the transmission of a message, the status indicating
that an IFR byte has been received is indicated in the BDLC_DLCBSVR register before an EOF is
indicated. Refer to
manage the reception of IFR bytes.
6-40
Loss of Arbitration
Error Detection
Transmitter Underrun
In-Frame Response to a Transmitted Message
Section 6.4.8, “Receiving An In-Frame Response (IFR),”
MPC5125 Microcontroller Reference Manual, Rev. 2
for a description of how to
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