MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 823

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

29.3.2.1
By default, from the release of RESET, the WDT is enabled. If the WDT is not needed, the user can disable
it by clearing the WDT_SWCRR[SWEN] bit. The WDT_SWCRR[SWEN] bit is cleared by the software
after a system reset to disable the WDT. When it is disabled, the watchdog counter and prescaler counter
are held in a stopped state. The WDT_SWCRR register is a write-once register; therefore, only software
can disable the WDT. After it is disabled, it can only be re-enabled by resetting the system.
If the WDT is not needed, the user must clear the WDT_SWCRR[SWEN] bit to disable it.
29.3.2.2
Without periodic software servicing, the WDT times out and issues a reset or a nonmaskable MCP
interrupt.
If the WDT_SWCRR[SWRI] bit is clear when the WDT times out, an MCP interrupt to the CPU core is
created. If the WDT_SWCRR[SWRI] bit is set when the WDT times out, a hardware reset is created.
29.3.2.3
The WDT counter clock can be prescaled by 1 or 65,536, depending up the setting of the prescale bit of
the WDT_SWCRR.
Freescale Semiconductor
•
— Reset mode (WDT_SWCRR[SWRI] = 1)
— Interrupt mode (WDT_SWCRR[SWRI] = 0)
WDT prescaled/non-prescaled clock mode
The WDT counter clock can be prescaled by programming the WDT_SWCRR[SWPR] bit that
controls the divide-by-65,536 of the WDT counter.
— Prescale mode (CRR[SWPR] = 1)
— Non-prescale mode (CRR[SWPR] = 0)
Prescale mode (WDT_SWCRR[SWPR] = 1 — The WDT counter clock uses a prescaler of 65,536.
Non-prescale mode (WDT_SWCRR[SWPR] = 0) — The WDT counter clock uses a prescaler of
1.
WDT causes a hardware reset.
WDT causes an MCP interrupt to the core.
The WDT clock is prescaled.
The WDT clock is not prescaled.
WDT Enable/Disable Mode
WDT Reset/Interrupt Output Mode
WDT Prescaled/Non-Prescaled Clock Mode
MPC5125 Microcontroller Reference Manual, Rev. 2
Software Watchdog Timer (WDT)
29-7