MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 894

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32-66
Total Bytes to
C-prog-mask
Transfer
µFrame
Status
29:26
25:16
15:8
IOC
Bit
7:0
31
30
P
Interrupt On Complete
0 Do not interrupt when transaction is complete.
1 Do interrupt when transaction is complete. When the host controller determines that the split transaction has
Page Select. Used to indicate which data page pointer should be concatenated with the CurrentOffset field to
construct a data buffer pointer
0 selects Page 0 pointer
1 selects Page 1 pointer
The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from
a 1 to a 0).
Reserved. This field reserved for future use and should be cleared.
Software initializes this field to the total number of bytes expected in this transfer. Maximum value is 1023
(3FFh)
Split complete progress mask. The host controller uses this field to record which split-completes have been
executed.
This field records the status of the transaction executed by the host controller for this slot. This field is a bit
vector with the following encoding:
Status Bit
completed, it asserts a hardware interrupt at the next interrupt threshold.
7
6
5
4
3
2
1
0
Active. Set by software to enable the execution of an isochronous split transaction by the host
controller.
ERR. Set by the host controller when an ERR response is received from the Companion
Controller.
Data Buffer Error. Set by the host controller during status update to indicate the host controller is
unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast
enough during transmission (under run). In the case of an under run, the host controller transmits
an incorrect CRC (thus invalidating the data at the endpoint). If an overrun condition occurs, no
action is necessary.
Babble Detected. Set by the host controller during status update when babble is detected during
the transaction generated by this descriptor.
Transaction Error (XactErr). Set by the host controller during status update in the case where the
host did not receive a valid response from the device (Time-out, CRC, Bad PID, etc.). This bit is
only set for IN transactions.
Missed Micro-Frame. The host controller detected that a host-induced hold- off caused the host
controller to miss a required complete-split transaction.
Split Transaction State (SplitXstate). The bit encodings are:
0 Do Start Split. This value directs the host controller to issue a start split transaction to the
1 Do Complete Split. This value directs the host controller to issue a complete split transaction to
Reserved. Bit reserved for future use and should be cleared.
endpoint when a match is encountered in the S-mask.
the endpoint when a match is encountered in the C-mask.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-53. siTD Transfer Status and Control
Description
Definition
Freescale Semiconductor