MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 339

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3.2.3
The High Priority Configuration Register (HIPRIO_CONFIG) controls the high priority detection logic.
The hiprio detection logic detects what percentage of the requests ACKed by the DRAM controller are
ACKed with a priority larger than eight.
1
Freescale Semiconductor
CLEAR_CONGEST_LEVEL[11:4] If(average_hipriority[12:4] < clear_congest_level[12:4]) → clear the congested flag.
Address: Base + 0x0088
SET_CONGEST_LEVEL[11:4]
AVERAGE_HIPRIORITY[12:0]
Refer to
Reset
Reset
FILTER BANDWIDTH[2:0]
W
W
R
R
Equation 12-1
16
0
0
0
BANDWIDTH
Field
High Priority Configuration Register (HIPRIO_CONFIG)
FILTER
17
0
0
1
Figure 12-4. High Priority Configuration Register (HIPRIO_CONFIG)
SET_CONGEST_LEVEL[11:4]
and
18
0
0
2
Equation 12-2
19
—
0
3
Average number of high priority requests to DRAM, coded between values 0x1000 and
If(average_hipriority[12:4] > set_congest_level[12:4]) → set the congested flag.
0x0000
0x1000: 100% high-priority requests.
0x0000: 0% high-priority requests.
This setting controls the averaging time of the filter used for average_hipriority[12:0]
000 Time constant W0 = 8 ACKS, K = 0.125
001 Time constant W0 = 16 ACKS, K = 0.0625
010 Time constant W0 = 32 ACKS, K = 0.0312
011 Time constant W0 = 64 ACKS, K = 0.0156
100 Time constant W0 = 128 ACKS, K = 0.0078
101 Time constant W0 = 256 ACKS, K = 0.0039
110 Time constant W0 = 512 ACKS, K = 0.0020
111 Time constant W0 = 1024 ACKS, K = 0.0010
Table 12-4. HIPRIO_CONFIG field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
—
20
4
0
for the relationship between filter bandwidth and filter behavior.
—
21
0
5
—
22
0
6
—
23
0
AVERAGE_HIPRIORITY[12:0]
7
—
24
8
0
Description
—
25
9
0
CLEAR_CONGEST_LEVEL[11:4]
Multi-port DRAM Controller Priority Manager
—
10
26
0
—
11
27
0
—
12
28
0
Access: User read/write
—
13
29
0
—
14
30
0
1
—
15
31
12-7
0