MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 853

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
ULPIE
NAKE
Field
SRE
URE
PCE
UEE
SLE
AAE
SEE
FRE
NAK Interrupt Enable
Software sets this bit if it wants to enable the hardware interrupt for the NAK Interrupt bit. If this bit and the
corresponding NAK Interrupt bit are set, a hardware interrupt is generated.
ULPI Enable
When this bit is a 1 and the ULPI interrupt bit in the USB_USBSTS register transitions, the controller issues
an interrupt. The interrupt is acknowledged by software writing a 1 to the ULPI Interrupt bit.
Used by both host and device controller.
Sleep Enable. This is a non-EHCI bit. When this bit is a 1 and the DCSuspend bit in the USB_USBSTS register
transitions, the OTG controller issues an interrupt. The interrupt is acknowledged by software writing a 1 to
the DCSuspend bit. Used only in device mode.
0 Disabled.
1 Enabled.
SOF Received Enable. This is a non-EHCI bit. When this bit is a 1 and the SOF Received bit in the
USB_USBSTS register is a 1, the controller issues an interrupt. The interrupt is acknowledged by software
clearing the SOF received bit.
0 Disabled.
1 Enabled.
USB Reset Enable. This is a non-EHCI bit present on the OTG module only. When this bit is a 1 and the USB
reset received bit in the USB_USBSTS register is a 1, the device controller issues an interrupt. The interrupt
is acknowledged by software clearing the USB reset received bit. Used only in device mode.
0 Disabled.
1 Enabled.
Interrupt on Async Advance Enable. When this bit is a 1 and the interrupt on async advance bit in the
USB_USBSTS register is a 1, the controller issues an interrupt at the next interrupt threshold. The interrupt
is acknowledged by software clearing the interrupt on async advance bit. Used only in host mode.
0 Disabled.
1 Enabled.
System Error Enable. When this bit is a 1 and the system error bit in the USB_USBSTS register is a 1, the
controller issues an interrupt. The interrupt is acknowledged by software clearing the system error bit.
0 Disabled.
1 Enabled.
Frame List Rollover Enable. When this bit is a 1 and the frame list rollover bit in the USB_USBSTS register is
a 1, the controller issues an interrupt. The interrupt is acknowledged by software clearing the frame list rollover
bit. Used only by the host mode.
0 Disabled.
1 Enabled.
Port Change Detect Enable. When this bit is a 1 and the port change detect bit in the USB_USBSTS register
is a 1, the controller issues an interrupt. The interrupt is acknowledged by software clearing the port change
detect bit.
0 Disabled.
1 Enabled.
USB Error Interrupt Enable. When this bit is a 1 and the USBERRINT bit in the USB_USBSTS register is a 1,
the controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software
clearing the USBERRINT bit in the USB_USBSTS register.
0 Disabled.
1 Enabled.
Table 32-18. USB_USBINTR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Universal Serial Bus Interface with On-The-Go
32-25