MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 373

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.5.6
The Ethernet Control (ETH_ECNTRL) register is a read/write user register; however, some fields may be
altered by hardware as well. The ETH_ECNTRL register enables/disables the FEC. The Reserved bits
must be cleared.
1
14.3.5.7
The MII Management Frame (ETH_MII_DATA) register does not reset to a defined value. The
ETH_MII_DATA register communicates with the attached MII-compatible PHY device, providing
read/write access to MII registers. Performing a write to the ETH_MII_DATA register causes a
management frame to be sourced, unless the ETH_MII_SPEED register has been programmed to 0.
Writing to ETH_MII_DATA when ETH_MII_SPEED equals 0, and the ETH_MII_SPEED register is then
written to a non-zero value, an MII frame is generated with the data previously written to the
ETH_MII_DATA register. This allows ETH_MII_DATA and ETH_MII_SPEED to be programmed in
either order if ETH_MII_SPEED is currently zero.
Freescale Semiconductor
Address: Base + 0x024
Reserved. Do not write. This bit must remain cleared.
ETHER_EN
Reset
Reset
RESET
Field
W
W
R
R
16
0
1
0
0
0
Ethernet Control (ETH_ECNTRL) Register
MII Management Frame (ETH_MII_DATA) Register
Ethernet enable. When this bit is set, the fast Ethernet controller is enabled, and reception and transmission
is possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad
CRC is appended to any frame currently being transmitted. The buffer descriptor(s) for an aborted transmit
frame are not updated following deassertion of ETHER_EN. When ETHER_EN is deasserted, the DMA,
buffer descriptor, and FIFO control logic are reset, including buffer descriptor and FIFO pointers. The
ETHER_EN bit is altered by hardware under the following conditions:
Ethernet controller reset. When this bit is set, the equivalent of a hardware reset is performed, but it is local
to the FEC. The ETHER_EN bit is cleared and all other FEC registers take their reset values. Also, any
transmission/reception currently in progress is abruptly aborted. This bit is automatically cleared by hardware
during the reset sequence. The reset sequence takes approximately 8 clock cycles after RESET is written with
a 1. It’s recommended to read ETH_ECNTRL register back and this can give enough time to go through reset
sequence
• If ETH_ECNTRL[RESET] is written to a 1 by software, ETHER_EN is cleared
• If error conditions occur, causing the EBERR bit of the ETH_IEVENT register to set, ETHER_EN is cleared.
17
0
1
0
0
1
18
0
1
0
0
2
Figure 14-7. Ethernet Control (ETH_ECNTRL) Register
19
0
1
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-10. ETH_ECNTRL field descriptions
20
4
0
0
0
0
0
21
0
0
0
5
1
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
Fast Ethernet Controller (FEC)
12
28
0
0
0
0
Access: User read/write
0
13
29
0
0
0
1
ETHE
R_EN
14
30
0
0
0
SET
14-17
RE-
15
31
0
0
0