MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 941

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.11 Split Transactions
USB 2.0 defines extensions to the bus protocol for managing USB 1.x data streams through USB 2.0 hubs.
This section describes how the host controller uses the interface data structures to manage data streams
with full- and low-speed devices, connected below a USB 2.0 hub, utilizing the split transaction protocol.
Refer to the USB 2.0 Specification for the complete definition of the split transaction protocol. Full- and
low-speed devices are enumerated identically as high-speed devices, but the transactions to the full- and
low-speed endpoints use the split-transaction protocol on the high-speed bus. The split transaction protocol
is an encapsulation of (or wrapper around) the full- or low-speed transaction. The high-speed wrapper
portion of the protocol is addressed to the USB 2.0 hub and transaction translator below that the full- or
low-speed device is attached.
EHCI uses dedicated data structures for managing full-speed isochronous data streams. Control, bulk, and
interrupt are managed using the queuing data structures. The interface data structures need to be
programmed with the device address and the transaction translator number of the USB 2.0 hub operating
as the low-/full-speed host controller for this link. The following sections describe how the host controller
processes and manages the split transaction protocol.
32.6.11.1 Split Transactions for Asynchronous Transfers
A queue head in the asynchronous schedule with an EPS field indicating a full-or low-speed device
indicates to the host controller that it must use split transactions to stream data for this queue head. All
full-speed bulk and full- and low-speed control are managed via queue heads in the asynchronous
schedule.
Software must initialize the queue head with the appropriate device address and port number for the
transaction translator serving as the full-/low-speed host controller for the links connecting the endpoint.
Software must also initialize the split transaction state bit (SplitXState) to Do-Start-Split. Finally, if the
endpoint is a control endpoint, system software must set the control transfer type (C) bit in the queue head
to a one. If this is not a control transfer type endpoint, the C bit must be initialized by software to be a zero.
The host controller uses this information to properly set the endpoint type (ET) field in the split transaction
bus token. When the C bit is a zero, the split transaction token's ET field is set to indicate a bulk endpoint.
When the C bit is a one, the split transaction token's ET field is set to indicate a control endpoint. Refer to
Chapter 8 of USB Specification, Revision 2.0 for details.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
32-113