MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 947

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

An example traversal of a periodic schedule that includes FSTNs is illustrated in
In frame N (micro-frames 0-7), for this example, the host controller traverses all of the schedule data
structures utilizing the normal path link pointers in any FSTNs it encounters. This is because the host
controller has not yet encountered a save-place FSTN so it is not executing in recovery path mode. When
Freescale Semiconductor
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•
•
•
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Micro-Frames 0, 1
Normal Traversal
Normal Traversal
Always follow the normal path link pointer when it encounters an FSTN that is a save-place
indicator. The host controller must not recursively follow save-place FSTNs. Therefore, while
executing in recovery path mode, it must never follow an FSTN's back path link pointer.
Do not process an siTD or iTD data structure; simply follow its next link pointer.
Do not process a QH (Queue Head) whose EPS field indicates a high-speed device; follow its
horizontal link pointer.
When a QH’s EPS field indicates a full/low-speed device, the host controller only considers it for
execution if its SplitXState is DoComplete (this applies whether the PID code indicates an IN or
an OUT). Refer to the EHCI Specification for a complete list of additional conditions that must be
met in general for the host controller to issue a bus transaction. The host controller must not execute
a start-split transaction while executing in recovery path mode. Refer to the EHCI Specification for
special handling when in recovery path mode.
Stop traversing the recovery path when it encounters an FSTN that is a restore indicator. The host
controller unconditionally uses the saved value of the save-place FSTN's normal path link pointer
when returning to the normal path traversal. The host controller must clear the context of executing
a recovery path when it restores schedule traversal to the save-place FSTN's normal path link
pointer.
If the host controller determines there is not enough time left in the micro-frame to complete
processing of the periodic schedule, it abandons traversal of the recovery path and clears the
context of executing a recovery path. The result is the host controller starts traversal at the frame
list at the start of the next consecutive micro-frame.
for Frame N+1
for Frame N
Figure 32-66. Example Host Controller Traversal of Recovery Path via FSTNs
Frame Numbers
N+5
N+4
N+3
N+1
N–1
N–2
N
8
8
8
8
8
8
8
8
3.0
2.0
7
6
5
4
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
8
8
3.1
2.1
Save = N
8
8
3.2
2.2
T-Int = 0
8
2.3
N-Ptr
B-Ptr
4
4
4
4
3
2
1
0
Universal Serial Bus Interface with On-The-Go
Causes Restore
to Normal Path
2
2
Traversal
1
0
Figure
N-Ptr
B-Ptr
Restore = N
Recovery Path
Traversal
32-66.
T-Int = 1
1
0
• • •
32-119