MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 973

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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There are other options suggested in the Transaction Translator section of the USB Specification Revision
2.0.
32.6.14.1.2 USB Interrupt (Interrupt on Completion (IOC))
Transfer descriptors (iTDs, siTDs, and queue heads (qTDs)) contain a bit that can cause an interrupt on
their completion. The completion of the transfer associated with that schedule item causes the USB
Interrupt (USBINT) bit in the USB_USBSTS register to be set. In addition, if a short packet is encountered
on an IN transaction associated with a queue head, this event also causes USBINT to be set. If the USB
interrupt enable bit in the USB_USBINTR register is set, a hardware interrupt is signaled to the system at
the next interrupt threshold. If the completion is because of errors, the USBERRINT bit in the
USB_USBSTS register is also set.
32.6.14.1.3 Short Packet
Reception of a data packet less than the endpoint's max packet size during control, bulk, or interrupt
transfers signals the completion of the transfer. When a short packet completion occurs during a queue
head execution, the USBINT bit in the USB_USBSTS register is set. If the USB interrupt enable bit is set
in the USB_USBINTR register, a hardware interrupt is signaled to the system at the next interrupt
threshold.
32.6.14.2 Host Controller Event Interrupts
These interrupt sources are independent of the interrupt threshold, with the one exception being the
interrupt on async advance.
32.6.14.2.1 Port Change Events
Port registers contain status and status change bits. When the status change bits are set, the host controller
sets the port change detect bit in the USB_USBSTS register. If the port change interrupt enable bit in the
USB_USBINTR register is set, the host controller issues a hardware interrupt. The port status change bits
are:
32.6.14.2.2 Frame List Rollover
This event indicates the host controller has wrapped the frame list. The current programmed size of the
frame list affects how often this interrupt occurs. (If the frame list size is 1024, the interrupt occurs every
1024 milliseconds. If it is 512, it occurs every 512 milliseconds, etc.) When a frame list rollover is
detected, the host controller sets the frame list rollover bit in the USB_USBSTS register. If the frame list
rollover enable bit in the USB_USBINTR register is set, the host controller issues a hardware interrupt.
This interrupt is not delayed to the next interrupt threshold.
Freescale Semiconductor
Connect Status Change
Port Enable/Disable Change
Over-current Change
Force Port Resume
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-145

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