MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 1005

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Appendix A
Memory Map
A.1
This appendix lists the memory-mapped registers and addresses for the MPC5125 device.
A.2
Freescale Semiconductor
0x0_0000–0_01FF
0x0_0200–0_08FF
0x0_0900–0_09FF
0x0_0A00–0_0AFF
0x0_0B00–0_0BFF
0x0_0C00–0_0CFF
0x0_0D00–0_0DFF
0x0_0E00–0_0EFF
0x0_0F00–0_0FFF
0x0_1000–0_10FF
0x0_1100–0_117F
0x0_1180–0_11FF
0x0_1200–0_12FF
0x0_1300–0_137F
0x0_1380–0_13FF
0x0_1400–0_14FF
0x0_1500–0_15FF
0x0_1600–0_16FF
0x0_1700–0_171F
0x0_1720–0_173F
0x0_1740–0_17FF
(0xFF40_0000)
Offset from
IMMRBAR
Introduction
MPC5125 Register Map
MPC5125 Microcontroller Reference Manual, Rev. 2, Release Candidate
Absolute offset
0xFF40_0C00
0xFF40_0D00
0xFF40_0A00
0xFF40_0B00
0xFF40_0E00
0xFF40_0F00
0xFF40_1400
0xFF40_1720
0xFF40_0000
0xFF40_0200
0xFF40_0900
0xFF40_1000
0xFF40_1100
0xFF40_1180
0xFF40_1200
0xFF40_1300
0xFF40_1380
0xFF40_1500
0xFF40_1600
0xFF40_1700
0xFF40_1740
1
Table A-1. MPC5125 memory map
System configuration (XLBMEN)
Reserved
Software watchdog timer (WDT)
Real time clock (RTC)
General purpose timer (GPT1)
Integrated programmable interrupt controller (IPIC)
CSB arbiter
Reset module (RESET)
Clock module (CLOCK)
Power management control (PMC)
General Purpose I/O (GPIO1)
General Purpose I/O (GPIO2)
Reserved
MSCAN1
MSCAN2
Byte data link controller (BDLC)
Secure digital host controller (SDHC1)
Reserved
Inter-integrated circuit (I
Inter-integrated circuit (I
Inter-integrated circuit (I
3
Region Name
2
2
2
C1)
C2)
C3)
Appendix A/A-1
Chapter 29/29-1
Chapter 27/27-1
Chapter 15/15-1
Chapter 18/18-1
Chapter 24/24-1
Chapter 16/16-1
Chapter 16/16-1
Chapter 22/22-1
Chapter 22/22-1
Chapter 28/28-1
Chapter 19/19-1
Chapter 19/19-1
Chapter 19/19-1
Section/Page
Chapter 8/8-1
Chapter 4/4-1
Chapter 5/5-1
Chapter 6/6-1
A-1
2