MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 564

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
LocalPlus Bus Controller (LPC)
Figure 21-23
synchronous bursts transactions.
(page mode) transactions. Detailed information about timing diagrams and the influence of register
settings can be found in the MPC5125 Microcontroller Data Sheet.
21-24
Note: Data1 is most significant byte and Data2 (2 byte transfer) or Data 4 (4 byte transfer) is lowest significant byte of data word.
Swap setting has no influence on byte transfers.
NO/YES
YES
YES
NO
NO
1
Note: Data1 is most significant byte and Data2 is lowest significant byte of data word.
WS or RS set
Swap setting has no influence on byte transfers.
1
NO/YES
Swap
YES
NO
shows a non-muxed transaction.
In the following five diagrams, deadcycle and holdcycle are each set to 0.
2 bytes
4 bytes
Table 21-26. Aligned Data Transfers for 32-Bit Data Bus Width (continued)
1 byte
1
Table 21-27. Aligned Data Transfers for 16-Bit Data Bus Width
Transfer
2 bytes
1 byte
Size
01
10
00
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 21-26
00
00
00
01
10
11
10
00
10
TSIZ0
1
0
Figure 21-24
and
NOTE
Figure 21-27
Data1
Data2
Data1
Data4
Data
—
—
—
—
—
Address 0
0
1
0
and
Figure 21-25
show non-muxed asynchronous burst
Data2
Data1
Data2
Data3
Data
—
—
—
—
—
AD[15:8]
Data1
Data2
Data
—
Data Lanes
show non-muxed
Data1
Data2
Data3
Data2
Data
—
—
—
—
—
Freescale Semiconductor
AD[7:0]
Data2
Data1
Data
—
Data2
Data1
Data4
Data1
Data
—
—
—
—
—