MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 717

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5.2.1
Freescale Semiconductor
Signal
TxD
IPB Interface to
the FIFOC
Block Diagram and Signal Definition for Codec Mode
Transmitter Serial Data Output. Data is shifted out on TxD on the falling or rising edge of the clock source.
Transfers can be specified as LSB or MSB first. TxD is held low when Tx is disabled or idle.
• Data shifted out on the rising edge of CLK if SICR[ClkPol] equals 0
• Data shifted out on the falling edge of CLK if SICR[ClkPol] equals 1
• Data send MSB first if SICR[SHDIR] equals 0
• Data send LSB first if SICR[SHDIR] equals 1
MCLK
Table 25-30. PSC Signal Description for Codec Mode
Figure 25-45. PSC Codec Interface in Slave Mode
PSC
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 25-44. PSC Codec Block Diagram
FRAME
PSC
CLK
RxD
TxD
BCLKDiv[0:15]+1
Generation
Clock
Unit
Description
Codec Device
SSYNC0
SCLK0
SRx0
STx0
External
Transmitter
Receiver
MCLK
Frame
BCLK
Programmable Serial Controller (PSC)
RxD
TxD
External
Interface
Signals
25-39