MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 940

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.10 Ping Control
USB 2.0 defines an addition to the protocol for high-speed devices called ping. Ping is required for all USB
2.0 high-speed bulk and control endpoints. Ping is not allowed for a split-transaction stream. This
extension to the protocol eliminates the bad side effects of NAKing OUT endpoints. The status field has a
ping state bit that the host controller uses to determine the next actual PID it uses in the next transaction
to the endpoint (see
that meet all of the following criteria:
Table 32-75
PING protocol. Refer to Chapter 8 in the USB Specification, Revision 2.0 for detailed description on the
Ping protocol.
The ping state bit is described in
on the initialization of the ping protocol (start in Do OUT when you don't know whether there is space on
the device or not). The host controller manages the ping state bit. System software sets the initial value in
the queue head when it initializes a queue head. The host controller preserves the ping state bit across all
queue advancements. This means when a new qTD is written into the queue head overlay area, the
previous value of the ping state bit is preserved.
32-112
•
•
•
The queue head is not an interrupt
The EPS field equals High-Speed
The PIDCode field equals OUT
illustrates the state transition table for the host controller's responsibility for maintaining the
Table
1
2
3
Transaction Error (XactErr) is any time the host misses the handshake.
No transition change required for the ping state bit. The stall handshake
results in the endpoint being halted (for example, active cleared and halt
set). Software intervention is required to restart queue.
A Nyet response to an OUT means that the device has accepted the data,
but cannot receive any more at this time. Host must advance the transfer
state and transition the ping state bit to do ping.
Current
Do OUT
Do OUT
Do OUT
Do OUT
Do OUT
Do Ping
Do Ping
Do Ping
Do Ping
32-59). The ping state bit is only managed by the host controller for queue heads
Table 32-75. Ping Control State Transition Table
MPC5125 Microcontroller Reference Manual, Rev. 2
Table
PING
PING
PING
PING
Host
OUT
OUT
OUT
OUT
OUT
32-59. The defined ping protocol allows the host to be imprecise
Event
XactErr
XactErr
Device
Nyet
Stall
Stall
Nak
Nak
Ack
Ack
1
1
Do Ping
Do OUT
Do OUT
Do Ping
Do Ping
Do Ping
Do Ping
Next
N/C
N/C
2
2
3
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