MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 723

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

data in the FIFO. Therefore, only the order in the FIFO defines whether the data was received or
transmitted during the high or low phase of the LRCK.
Table 25-34
SICR[GenClk] must be cleared and the configuration of the
25.5.2.6
The PSC supports a full duplex SPI interface. This mode is chosen by setting SICR[SPI] equal to 1, which
must be true for the MSTR, CPOL, CPHA, and UseEOF bits in the SICR register to take effect. In SPI
mode, the SICR[SIM] bits must also be set to select the data width. To configure the PSC to act like an
SPI master, set SICR[MSTR] equal to 1 or set SICR[MSTR] equal to 0 to configure the PSC as an SPI
slave. When the SICR[MSTR] bit is set, SICR[GenClk] must also be set to 1 because the PSC is driving
the SPI clock line. When SICR[MSTR] equals 0, SICR[GenClk] must be set to 0 because the external SPI
is driving the SCK clock line. The CPOL and CPHA bits in the SICR register operate exactly the same
Freescale Semiconductor
Register
SICR
CCR
CR
CR
•
•
•
•
•
•
•
Use PSC1 as I2S master
32-bit data, MSB first
SCLK frequency 1 MHz
FrameSync width 40 bits
Data shifted out on the falling edge of SCLK
Data transfer starts one CLK cycle after the FrameSync is active
Frame starts with LRCK low
LRCK (Frame)
SCLK (CLK)
0x2FE0_0000 Select the 32-bit Codec I2S master mode, MSB first, DTS1 = 1
0x270F_0000 Set the FrameSync width (40 bit) and SCKL frequency
shows an example of how to configure the PSC1 as I2S master. For the slave mode the bit
SDATA
Transmitting and Receiving in SPI Mode
Value
0x0A
0x05
Start of Frame
Disable the Tx and Rx part for configuration if the PSC was enabled by the work before.
Enable Tx and Rx
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-34. 32-bit I2S Master Mode for PSC1
DTS1
Figure 25-49. I2S-Data Transmission
Data Width
Frame Length
Figure 25-49
CCR
Setting
Empty Data Bits until the
New Data Starts (Zero)
register can be ignored.
shows the I2S transmission diagram.
Programmable Serial Controller (PSC)
Start of Frame
25-45