MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 115

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.1.6
The Shadow of System Clock Control Register 2 (SCFR2S), shown in
SYS_DIV ratio. When this register gets a control signal from the Power Management Control Module
(PMC) to update the main SCFR2, the value of this shadow register overwrites the SCFR2.
Freescale Semiconductor
SDHC1_DIV SDHC1 Divide Ratio
SDHC2_DIV SDHC2 Divide Ratio
SYS_DIV
Field
Shadow of System Clock Frequency Register 2 (SCFR2S)
SYS_CLK Divide Ratio
Note: Only even integer divide ratios are supported.
Note: Only even integer divide ratios are supported.
Divide Factor
2.5
3.5
4.5
10
2
3
4
5
6
7
8
9
CSB_CLK:SDHC_CLK
CSB_CLK:SDHC_CLK
Bit Encoding
MPC5125 Microcontroller Reference Manual, Rev. 2
00_0000
00_0001
00_0010
00_0011
00_0100
00_0101
00_0110
00_1000
00_0111
00_1001
00_1010
00_1100
n/4
n/4
62
62
2
4
6
2
4
6
Table 5-10. SCFR2 field descriptions
Divide Factor
0b1111_1000 (248d)
0b1111_1000 (248d)
11
12
13
14
15
16
17
18
19
20
21
22
0b0001_0000 (16d)
0b0011_0000 (24d)
0b0001_0000 (16d)
0b0011_0000 (24d)
0b0000_1000 (8d)
0b0000_1000 (8d)
Field value
Field value
Description
n
n
Bit Encoding
00_1011
00_1101
00_1110
01_0000
00_1111
01_0001
01_0010
01_0100
01_0011
01_0101
01_0110
01_1000
All other settings are reserved.
Divide Factor
Figure
23
24
25
26
27
28
29
30
31
32
33
5-11, programs the
Clocks and Low-Power Modes
Bit Encoding
01_0111
01_1001
01_1010
01_1100
01_1011
01_1101
01_1110
10_0000
01_1111
10_0001
10_0010
5-15