MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 18

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Chapter 9, “Direct Memory Access (DMA),”
MPC5125.
Chapter 10, “Display Interface Unit (DIU),”
implemented on the MPC5125.
Chapter 11, “DRAM Controller,”
Mobile-DDR, DDR-1, DDR-2, and SDR memories.
Chapter 12, “Multi-port DRAM Controller Priority Manager,”
the DRAM controller.
Chapter 13, “External Memory Bus (EMB),”
External Memory Bus.
Chapter 14, “Fast Ethernet Controller (FEC),”
programming model of the FEC block.
Chapter 15, “General Purpose Timers (GPT),”
perform general purpose timer and general purpose I/O (GPIO) functions.
Chapter 16, “General Purpose I/O (GPIO),”
pin descriptions, register settings and interrupt capabilities.
Chapter 17, “IIM/Fusebox,”
programming information stored in on-chip fuse elements.
Chapter 18, “Integrated Programmable Interrupt Controller (IPIC),”
hardware interrupts for the MPC5125 device.
Chapter 19, “Inter-Integrated Circuit (I2C),”
clock synchronization, and I
Chapter 20, “I/O Control,”
the pads.
Chapter 21, “LocalPlus Bus Controller (LPC),”
MPC5125.
Chapter 22, “MSCAN,”
CAN protocol according to Bosch Specification version 2.0B.
Chapter 23, “NAND Flash Controller (NFC),”
memory devices.
Chapter 24, “Power Management Control Module (PMC),”
provide voltage control for the internal logic of the device.
Chapter 25, “Programmable Serial Controller (PSC),”
modes.
Chapter 26, “PSC Centralized FIFO Controller (FIFOC),”
controller for the PSC modules.
Chapter 27, “Real Time Clock (RTC),”
Chapter 28, “Secure Digital Host Controller (SDHC),”
Multimedia Cards (MMC), Secure Digital (SD) memory cards, and I/O cards.
Chapter 29, “Software Watchdog Timer (WDT),”
software errors by periodically issuing a reset unless interrupted by software.
MPC5125 Microcontroller Reference Manual, Rev. 2
describes the CAN module, a communication controller implementing the
describes the controls for the functional muxing and configuration of
2
describes the module that provides an interface for reading and
C programming model registers.
describes the multi-port DRAM controller that supports
describes the real time clock.
describes the general purpose I/O module, including
describes the Display Interface Unit (DIU)
describes the I
describes how the LPC and the NFC share the
describes the DMA controller implemented on the
describes the feature set, operation, and
describes eight independent timer channels that
describes the interface to standard NAND flash
describes the external bus interface of the
describes the counter that guards against
describes the UART, AC97, Codec, and I
describes the module that interfaces to
describes the centralized FIFO
2
describes the power blocks that
C module, including I
describes the priority manager for
summarizes the software and
Freescale Semiconductor
2
C protocol,
2
S