MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 252

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
9-32
MAJOR.LINKCH[5:0] Link channel number
BITER.LINKCH [5:0]
BITER.E_LINK
BITER[14:9]
BITER[8:0]
BWC[1:0]
Field
or
Enable channel-to-channel linking on major loop complete. This is the initial value copied into the
Beginning major iteration count. This is the initial value copied into the CITER field or ciTer.LINKCH field
CITER.E_LINK field when the major loop is completed. The CITER.E_LINK field controls channel linking
during channel execution. This bit must be equal to the CITER.E_LINK bit otherwise a configuration error
is reported.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Beginning major iteration count or beginning link channel number. This is the initial value copied into the
CITER field or CITER.LINKCH field when the major loop is completed. The CITER fields controls the
interation count and linking during channel execution.
If TCD.BITER.E_LINK equals 0,
No channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. TCD
word 5, bits [30:25] are used to form a 15-bit BITER field.
or
After the minor loop is exhausted, the DMA_ENGINE initiates a channel service request at the channel
defined by BITER.LINKCH[5:0] by setting that channel’s TCD.START bit.
The value contained in BITER.LINKCH[5:0] must not exceed the number of implemented channels.
when the major loop is completed. The CITER fields controls the interation count and linking during
channel execution.
This 9- or 15-bit count represents the beginning major loop count for the channel. As the major iteration
count is exhausted, the contents of the entire 16-bit BITER entry is reloaded into the 16-bit CITER entry.
When the BITER field is initially loaded by software, it must be set to the same value as that contained in
the CITER field.
If the channel is configured to execute a single service request, the initial values of BITER and CITER
should be 0x0001.
Bandwidth control. This two-bit field provides a mechanism to effectively throttle the amount of bus
bandwidth consumed by the DMA. In general, as the DMA processes the inner minor loop, it continuously
generates read/write, read/write, etc. sequences until the minor count is exhausted. This field forces the
DMA to stall after the completion of each read/write access to control the bus request bandwidth seen by
the platform’s cross-bar arbitration switch. To minimize start-up latency, bandwidth control stalls are
suppressed for the first two AHB bus cycles and after the last write of each minor loop.
The dynamic priority elevation setting elevates the priority of the DMA as seen by the cross-bar arbitration
switch for the executing channel. Dynamic priority elevation is suppressed during the first two AHB bus
cycles.
00 No DMA_ENGINE stalls.
01 Dynamic priority elevation.
10 DMA_ENGINE stalls for four cycles after each r/w.
11 DMA_ENGINE stalls for eight cycles after each r/w.
If TCD.MAJOR.E_LINK equals 0, no channel-to-channel linking (or chaining) is performed after the outer
major loop counter is exhausted.
or
After the major loop counter is exhausted, the DMA_ENGINE initiates a channel service request at the
channel defined by MAJOR.LINKCH[5:0] by setting that channel’s TCD.START bit.
The value contained in MAJOR.LINKCH[5:0] must not exceed the number of implemented channels.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-29. TCDn Word 7 field descriptions
Description
Freescale Semiconductor