MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 739

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
26.2.1
26.2.1.1
Freescale Semiconductor
Address: Base + 0x80 (PSCn_TX_CMD)
(0xFF41_1F00)
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
FIFOC_BASE
Reset
Reset
Offset from
0x14–0xFF
Field
EOF
0x0C
W
W
0x00
0x04
0x08
0x10
R
R
Base + 0xC0 (PSCn_RX_CMD)
16
0
0
0
0
0
Register Descriptions
Command Register (CMD)
1
End of Frame. This bit is set by writing a 1 to this bit field, writing zero will be ignored. The next write access
to the TX data register (PSCn_TX_DATA) will clear this bit.
0 The next data word is a normal data word.
1 Defines the next data word written to the data register as the last word of this frame.
17
0
0
0
0
1
FIFOC Command Register (FIFOC_CMD)
FIFOC interrupt register (FIFOC_INT)
FIFOC DMA request register (FIFOC_DMA)
Reserved
FIFOC debug register (FIFOC_DEBUG)
Reserved
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 26-2. Command Register (CMD)
20
4
0
0
0
0
Table 26-4. CMD field descriptions
Table 26-3. FIFOC memory map
Register
21
0
0
0
0
5
22
0
0
0
0
6
EOF
23
0
0
0
0
7
Description
SLICE
SET
RE
24
8
0
0
0
0
25
9
0
0
0
0
Chapter 2, “System Configuration and Memory
10
26
Access Reset Value
0
0
0
0
R/W
R/W
PSC Centralized FIFO Controller (FIFOC)
R
R
11
27
0
0
0
0
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
12
28
0
0
0
0
Access: User read/write
DMA
_EN
13
29
0
0
0
26.2.1.10/26-12
26.2.1.11/26-13
26.2.1.12/26-13
26.2.1.13/26-14
Section/Page
14
30
0
0
0
0
SLICE
_EN
15
31
26-5
0
0
0