MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 388

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.25 Receive Buffer Size (ETH_R_BUFF_SIZE) Register
The Receive Buffer Size (ETH_R_BUFF_SIZE) register dictates the maximum size of all receive buffers.
Only bits 21 – 27 are used, because receive frames are truncated at 2 KB – 1 bytes. This value should take
into consideration that the receive CRC is always written into the last receive buffer. To allow one
maximum-sized frame per buffer, the R_BUFF_SIZE bitfield must be set to ETH_R_CNTRL[MAX_FL]
or larger. The value of the ETH_R_BUFF_SIZE register must be evenly divisible by 16. To ensure this,
bits 3–0 are forced to 0. To minimize bus utilization (descriptor fetches), it is recommended that
ETH_R_BUFF_SIZE be greater than or equal to 256 bytes.
The ETH_R_BUFF_SIZE register is not affected by reset and must be initialized.
14.3.5.26 DMA Function Control (ETH_DMA_CONTROL) Register
The DMA Function Control (ETH_DMA_CONTROL) register contains the function code and byte order
fields used during each transfer between the DMA and the FEC interface. These bits can be written/read
by the user. This register should be programmed only when the ETHER_EN bit of the ETH_ECNTRL
register equals 0.
14-32
Address: Base + 0x188
R_BUFF_SIZE This is the receive buffer size.
Reset
Reset
Field
W
W
R
R
16
0
0
0
0
0
17
0
0
0
0
1
Figure 14-26. Receive Buffer Size (ETH_R_BUFF_SIZE) Register
18
0
0
0
0
2
Table 14-30. ETH_R_BUFF_SIZE field descriptions
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
—
21
0
0
5
—
22
0
0
6
—
23
0
0
7
R_BUFF_SIZE
Description
—
24
8
0
0
—
25
9
0
0
—
10
26
0
0
—
11
27
0
0
—
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
—
13
29
0
0
0
—
14
30
0
0
0
15
31
0
0
0
0