MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 471

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
18.2.1.11 System Mixed Interrupt Group A Priority Register (IPIC_SMPRR_A)
The System Mixed Interrupt Group A Priority Register (IPIC_SMPRR_A), shown in
defines the priority between DIU, DMA2, IRQ0, and IRQ1.
Freescale Semiconductor
Address: Base + 0x2C
Address: Base + 0x30
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (IPIC_SEMSR[SIRQ0] = 0).
These bits reflect the state of external IRQ pins. User should take care to drive all IRQ inputs to an inactive state prior to reset
negation.
Reset
Reset
Reset
Reset
Field
IRQ0
IRQ1
W
W
W
W
R
R
R
R
IRQ0
16
16
0
0
0
1
0
0
Note
Figure 18-14. System Mixed Interrupt Group A Priority Register (IPIC_SMPRR_A)
1
MIXA0P
MIXA4P
IRQ0 external interrupt source. When an interrupt is received, the interrupt controller sets the corresponding
IPIC_SEPNR bit.
When a pending interrupt is managed, clear the corresponding IPIC_SEPNR bit. For level triggered case, s/w
needs to negate the IRQx that automatically clears the bit in IPIC_SEPNR, and for edge triggered case, s/w
needs to clear IPIC_SEPNR.
IPIC_SEPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register,
writing zeros to this register has no effect.
Note: The IPIC_SEPNR bit positions are not changed according to their relative priority.
IRQ1 external interrupt source.
IRQ1
2
17
17
0
0
0
0
1
Figure 18-13. System External Interrupt Pending Register (IPIC_SEPNR)
1
18
18
0
0
0
0
0
0
2
2
19
19
0
0
0
0
0
1
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-14. IPIC_SEPNR field descriptions
MIXA1P
MIXA5P
20
20
4
0
0
0
0
4
0
0
21
21
0
0
0
0
1
1
5
5
22
22
0
0
0
0
0
1
6
6
MIXA2P
MIXA6P
23
23
0
0
0
0
1
1
7
7
Description
24
24
8
0
0
0
0
8
0
0
Integrated Programmable Interrupt Controller (IPIC)
25
25
9
0
0
0
0
9
0
1
MIXA3P
MIXA7P
10
26
10
26
0
0
0
0
1
1
11
27
11
27
0
0
0
0
1
1
12
28
12
28
0
0
0
0
0
0
0
0
Access: User read/write
Access: User read/write
Figure
13
29
13
29
0
0
0
0
0
0
0
0
18-14,
14
30
14
30
0
0
0
0
0
0
0
0
18-23
15
31
15
31
0
0
0
0
0
0
0
0